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Consider the design of a CMOS compound OR-OR-AND-INVERT (OA122) gate computing F-A+ B)-(C + D). a) sketch a transistor-level schematic b) sketch a stick diagram c) estimate the area from the stick diagram d) layout your gate with a CAD tool using unit-sized transistors e) compare the lavout size to the estimated area 1.17
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Answer #1

1-17〉 rans is /or 0(d) Design of Layout is not possible without proper tool as well as proper technology details. But I hope that you will be able to make the layout from the stick diagram.

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