Question

Change this code to implement a 2-input XOR gate starting from two AND gates, two inverters, and one OR gate. module Full Adder ( input X1, X2, Cin, output s, Cout) wire al, a2, a3; xor ul (al,X1,X2) and u2 (a2,x1,x2); and u3 (a3,al,cin) or u4 (Cout,a2,a3); xor u5 (S,al,cin); endmodule

Answer 1

Verilog code for your gate:

Module xor (input a, b: output f): wire a bar, b bar, W1, W2: not g_1 (a bar, a) not g_2 (b bar, b): and g_3 (W1, a bar, b): and g_4 (W2, b bar, a): or g_5 (f, W1, W2): end module