Question

Question#2: [ABET S.O. D] (6marks) Design control unit that generates a signal from a 4 unit-sized inverter. The signal must drive unit-sized loads in each bitslice of a 64-bit datapath. You can add inverters to buffer the signal to drive the large load. Assuming polarity of the signal does not matter, What is the best number of inverters to add and what delay can be achieved? How many stages should a path use?

Answer 1

Initial Drivers +64 + +64 +64 +64 + + + Datapath Loads N: 1 2 3 f 64 8 4 D: 65 18 15 - 4 2.8 15.3

Question 2 : The above figure shows the cases of adding 0,12,01 3 inverters. The path electrical effort is G=1, independent of the number of inverters. Thus, the path elfort is f= 64. The inverter Sizes are chosen to achieve equal stage effort, the total delay is D=N/64+N. - The Three stage design is fastest an fear superior to a single stage. If an even number of Inversions were required, the two on four stage designs are pomising. The fourstage design is slightly faster, but two stage design requires significanity less area and power.

Question #3: Now since the effective resistance of pmos transistor is 3 times as much as amos transistor the sizing of the NAND and NOR gates will be different first for a NAND gate recall that the pull down network was two series of nmos transistor so in order to have the same fall resistance as the inverter the width have to be twice the whit width. Now we sees NAND gates. MANDRig = 5/4 NOR 29 = 74. The Inverter has 3it en ratio and 4 units of capacitance. The NAND has a 3:2 ratio and 5 units of capacitance, while the NOR has a 6:1 ratio and yunits of capacitance,