Question

CMOS Design Styles Quiz Problem 1:

a) What is the typical "topology" for pMOS and nMOS in digital circuitry?

-pMOS Vdd to Vout, nMOS Vout to Gnd

-nMOS Vdd to Vout, pMOS Vout to Gnd

-pMOS Vdd to Gnd, nMOS Vin to Vout

-Only use xMOS

-Both transistors Vin to Vout

b) How do you implement nMOS in AND functions?

-series connected, with increased widths

-Parallel connected, with standard widths

-Series connected with half the widths

-Parallel connected, alternating large and small width

-Must use pMOS instead, becuase the topology is inverse with product functions

c) How could you most easily change a NAND gate into an AND?

-Add an inverter at the output

-Add an inverter in parallel with the control input

-Tie the inputs together

-Add 2 more pMOS in parallel

-Couple it with an OR gate, as long as the load capacitance is large enough

d) Should you panic if you find that a complement signal is need for an input?

-No, because the complement may be available already, or you can add an inverterin the worst case

-Yes, because you'll run out of inverters too quickly

-Yes, because that will take up all your extra space on the Si surface

-No, becuase you can just bypass that step

-No, because you can always leave it for the engineer on the next shift

e) What do you expect to happen if you accidentally hook the Clk signal to the inverter input?

-Output will switch twice in each clk cycle

-Output will latch to logic 1

-The control imput will be confused, resulting in an unknown logic output state

-The power supply may burn up becuase the unconnected signal line may touch Gnd

-The load capacitance will rise too high, preventing the output switching

f) In a dynamic logic gate, what is the Vout value prior to the Evaluate cycle?

-Logic 1

-Logic 0

-Z-state

-Undefined logic state

-Depends upon whether both pMOS and nMOS are in z-state or not

g) What is an adverse effect of having extra transistors in the logic?

-Increase in parasitic load capacitance

-Decrease in parasitic load capacitance

-Longer time for signal to get from Vdd to Gnd

-Longer time for signal to get from Gnd to Vdd

-Slower feedback response from Vin to Vout'

h) Standard XOR gates require 12 transistors. Is there a way to design with fewer transistors?

-Design with intervers and passgates

-No

-Design with OR instead of NOR gates

-Design with AND instead of NAND gates

-Discharge Vout prior to permitting the inverter feedbak to pMOS, thus causing the inductance of CL to kick back to Vin