Question

BlOCK.OP Block 10: PC; FUNCTION: write [PC] to the register P, 0] Problem E. The time taken for each one of the five classic stages of RISC instructions is listed as below. IF 200ps ID (Reg Read) 100ps EX(ALU Op) 150ps MEM (Data Access) 250ps WB (Reg Write) 100ps (There is more o

just h)

Answer 1

Here, pipeline speed up in ideal condition = 5 Now, let�s talk about speedup here. Here, total # of instructions = 400 Execution time in non-pipeline: - For LOR instruction, time required = 100 times (200 + 100 + 150 + 250 + 100) = 100 times 800 = 80000 ps for STR instruction, time required = 100 times (200 + 100 + 150 + 250) = 70000 ps For ADD instruction, time required = 100 times (200 + 100 + 150 + 100) = 55000 ps For BLT instruction, time required = 100 times (200 + 100 + 150) = 45000 ps overall time in case of non-pipeline = 80000 + 70000 + 55000 + 45000 = 150000 + 100000 = 250000 ps \r\n In case of pipeline, all the instructions which doesn�t require any particular stage, we insert MOP (do nothing on that stage). Also, in pipeline the input is more important than output.