Question

2. A digital clock signal is basically a square wave signal with 50% duty cycle. The frequency of the clock can be anything as needed by the digital circuit that is using it. Clock is used for timing and synchronization of digital circuits. Many times, there is a requirement to slow down the frequency of clock to a certain level and this can be done using clock frequency dividers EE200 Digital Design Laboratory Manual (reducing the frequency of clock or in other words slowing down the clock). For example, the onboard 100MHz clock in Digilent Nexus 4 FPGA board is too fast to run seven segment display as it requires at most 1kHz and at minimum 60Hz clock signal to operate. In this case if onboard 100MHz clock is utilized for running the seven segment display, it should be first slowed down to these limits, which can be easily done using clock frequency divider. The following example in Figure 5.6 gives a Verilog program of frequency divider the division factor is 4