Question

·20) |19) 118) 117) 116) 115) Question 1.(20 points, I point each. Put answers into the above table) 13)一114) 2)- ) S-bit signed binary data can represent the decimal values from 0 to 256 2) 10111 is the two's complement representation of b. False a. True a. -23 b.-9 c.-7 d. +22 e.+7 3) 01110 is the two's complement representation of a.-13 b.-15 c.-9 d.+14 e.+18 a.A. b, B, c.A+B d, B c, (AB). a. Trueb. False a. True a. 0110b. 110 c 100 d. 1010 a. Astable circuit Simplify ing A'B+A B' yields which of the following expressions? 5) Any fanction can be implemented by using only NOR gates 6) We are able to eliminate all the logic hazards in the combinational logic design. 7) Ifa 4-bit input data A: 0110 goes through an inverter, what is the output value? 8) Ring-oscillator is an element that is built with: 4) b. False b. Monstable circuit c.Bistable circuit For a synchronous sequential logic circuit, which of the following statement(s) is (are) true? 9) a Every circuit element is either a register or a combinational circuit b.At least one circuit clement is a register c. All registers receive the same clock signal d. Every cyclic path contains at least one register e. None of the above f. All of the above 10) A Moore FSM usually has a simpler circuit for its output(s) than that of Mealy FSM. 11) The clock skew is the total time for which the imput of a circuit must remain stable. 12) The number of select lines in an 8:1 multiplexer is equal to the number of input lines a. True b. False a. Trueb. False in a 3:8 decoder 13) An arithmetic left shift is a special case of division. 14) Arithmetic shift left is the same as logical shift left. 15) If we want to achieve A-B, it is more convenient to use a half adder instead of using a a. Trueb. False a. True b. False a. True b. False full adder

Answer 1

False Represented the signal number 8 bit signed binary represented 0 to 128 - 9 1 0 111 01001 = (9)_10 option - e (+ (8) 01110 10010 = (18)_10 A A B + A B A (B + B) = A \r\n false can be implementing using both NAND NOR gates False in sequential logic we can eliminate (c) 1001 n = 0110 1001 inverter (c) Bistable circuit Rins oscillator (c) all resisters receive the same clock signed (a) True moose Rightarrow inputs depends upon the present value moory Rightarrow inputs + output will be effected \r\n (a) True clock skew definition given True s: 1 Mux Rightarrow 2^3 : 1 Rightarrow selected line 3: 8 decodes Rightarrow 3 inputs False left shift mean Rightarrow multiplication Rightarrow shift means Rightarrow division false it is