Question

Why recommends control signals in modules be coded so they are active high? ( in Xilinx) ( Verilog and FPGA design)

Answer 1

This is recommended to done away with the RTL issues.

One designer chooses Active high for one module another designer chooses active low for another module, for the same reset signal. Simulations are all passed as done by RTL enginner, A lot of ambiguity gets developed when the FPGA design is tested and one module always goes into reset. To avoid and surprises, always use active-high.

Another aspect:
Also, active low signals requires an inversion (which subsequently adds a LUT in the path) before they can directly drive the control port of a register. And, by using extra LUTs and routing resources in case of active low signals, we would create timing problems and consume more power. Also, if you're using the active low clocks, you would require extra LUT for each clock, this would create the unnecessary requirement of more and more LUTs in total and make the design more power sinking. Better avoid it, please. :)