Question

Xilinx recommends control signals in modules be coded so they are active high. Why? (note: in Verilog and FPGA design)

Answer 1

Answer 1)

Xilinx recommends to use the control signals as active high, such that there is no coding errors are observed after the design is ready. This is only recommendation from Xilinx team but not an compulsion.

Example of the coding error can be, suppose of the top level module uses the active high control signal and the signal is taken during the hierarchy small module is created as active low signal, then it will be very difficult to catch this kind of erroe in the design. So, Xilinx always recommends to us active high control signal for saving the debug time. If one is comfortable in using proper polarity of signal throughout the design then there is no issue using active low or active high signal.