Question

Design JK, SR, D and T flip-flop with their Truth table, characteristic table and excitation table

Answer 1

Circuit Diagram SR Flipflop:

S (Set) 1- X oQ 0 A ou 0 B Y R(Reset) Circuit

The Set State

In the above diagram, when the input R is set to false or 0 and the input S is set to true or 1, the NAND gate Y has an input 0, which will produce the output Q' 1. The value of Q' is faded to the NAND gate 'X' as input 'A', and now both the inputs of the NAND gate 'X' are 1(S=A=1), which will produce the output 'Q' 0.

Now, if the input R is changed to 1 with 'S' remaining 1, the inputs of NAND gate 'Y' is R=1 and B=0. Here, one of the inputs is also 0, so the output of Q' is 1. So, the flip flop circuit is set or latched with Q=0 and Q'=1.

Reset State

The output Q' is 0, and output Q is 1 in the second stable state. It is given by R =1 and S = 0. One of the inputs of NAND gate 'X' is 0, and its output Q is 1. Output Q is faded to NAND gate Y as input B. So, both the inputs to NAND gate Y are set to 1, therefore, Q' = 0.

Now, if the input S is changed to 0 with 'R' remaining 1, the output Q' will be 0 and there is no change in state. So, the reset state of the flip flop circuit has been latched, and the set/reset actions are defined in the following truth table:

R State Set 0 OP S 1 1 0 1 Q 0 0 1 1 1 1 1 1 Q 1 1 0 0 1 Reset Description Set Q'>>1 No change Reset Q'>> No change Invalid Condition Invalid 0 0

Circuit Diagram JK Flipflop:

SR Flip-Flop Toggles on leading edge of clock signal S Clko lo ко- Circuit

In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K. It means the J and K input equates to S and R, respectively.

The two 2-input AND gates are replaced by two 3-input NAND gates. The third input of each gate is connected to the outputs at Q and Q'. The cross-coupling of the SR flip-flop permits the previous invalid condition of (S = "1", R = "1") to be used to produce the "toggle action" as the two inputs are now interlocked.

If the circuit is "set", the J input is interrupted from the "0" position of Q' through the lower NAND gate. If the circuit is "RESET", K input is interrupted from 0 positions of Q through the upper NAND gate. Since Q and Q' are always different, we can use them to control the input. When both inputs 'J' and 'K' are set to 1, the JK toggles the flip flop as per the given truth table.

Truth Table:

Input Description Same as for SR Latch Clock clk х Х Memory no change Reset Q>>0 J 0 0 0 0 1 1 1 1 Х к 0 0 1 1 0 0 1 1 Output Q ' 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 Set Q>>1 Х Toggle action X Toggle

Circuit Diagram for D flipflop:

S Data CIK R Gated SR Flip-Flop Inverter

We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and another to "RESET" the output. By using an inverter, we can set and reset the outputs with only one input as now the two input signals complement each other. In SR flip flop, when both the inputs are 0, that state is no longer possible. It is an ambiguity that is removed by the complement in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would change and become reset. However, this would be pointless since the output of the flip flop would always change on every pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip flop's latching circuitry. When the clock input is set to true, the D input condition is only copied to the output Q. This forms the basis of another sequential device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set to 1. So it will not change the state and store the data present on its output before the clock transition occurred. In simple words, the output is "latched" at either 0 or 1.

Truth Table for the D-type Flip Flop

D Clock » Q Q g' Q' X Description Memory no change Reset Q » 0 Set Q » 1 0 0 11 1 » 1 1 0 1 1

Circuit diagram for T flipflop:

The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of the "JK Flip Flop" are connected as a single input T. Below is the logical circuit of the T Flip Flop" which is formed from the "JK Flip Flop":

(J) T- Clk- -o (K)

Truth Table of T Flip Flop

Previous Next T 0 0 1 1 Q 0 1 0 1 Q' 1 0 1 0 Q 0 1 1 0 Q' 1 0 0 1