Question

^{FA Do 0 4x MUX TA Di 4x MUX FA 0 4x1 MUX FA 04x 1 MUX Figure 4.9 4-bit arithmetic circuit TABLE 4-4 Arithnetic Circuit Function Table Input Output Microoperation Add Add with carry Subtract with borrow Subtract Transfer A Increment A Decrement A Transfer A 0 01 D=A D=A+1 DA-1 D=A}

Answer 1

Features of ALU
We have designed the 4-Bit ALU which certain features as follows:

• Low-power CMOS Process Technology
• Total 16 arithmetic operations (add, subtract, plus, shift, plus 12 others)
• Total 16 logic operations (XOR, AND, NAND, NOR, OR, plus 11 others)
• Capable of active-high and active-low operation.
• Full carry look-ahead for high-speed arithmetic operation.
• Arithmetic operations expressed in 2s complement notation.
• 4 selection lines are to perform the operations on two 4 bit inputs in both the units.
• The 5th select line is used to select either one of the units.

Register Transfer Language • A register transfer language is a notation used to describe the microperation transfers between registers. • It is a system for expressing in symbolic form the microoperation sequences among register that are used to implement machine-language instructions.

From a register to bus: BUS-R Register B | Regis erd Re Register D Register A Bus lines Register Selected Register C Register D Register A Register B 0 B4 C4D4 0 B1C1 D1 0 4* 4 x1 MUX 4 x1 MUX 4x1 MUX MUX el 4-line bus

Major Parts of ALU
• Arithmetic block: This block is used to perform arithmetic operations such as addition, subtraction and comparison. The core of the arithmetic block is an adder. In the architecture presented in Figure 4.1, the adder uses carry look-ahead and sum-select techniques.
• Logic block: This block is used to perform simple bitwise logic operations such as AND (masking), OR and XOR, XNOR, NAND, NOT and etc.
• Multiplexers: These blocks are used to select the appropriate inputs for the arithmetic and logic blocks. Usually more than two buses arrive at the inputs of the ALU. Sometimes these multiplexers are used to perform some simple logic operations. The 2:1 MUX can be programmed to invert one of the operands (this can be used to execute a subtraction using just an adder).

Arithmetic Microoperations ARITHMETIC CIRCUIT AO CO DO FA S0 0 4x1 BO YO C1 MUX A1 X1 FA D1 S0 0 4x1 B1 Y 1 C2 A2 X2 C2 D2 FA S0 0 4x1 B2 Y2 C3 АЗ X3 C3 D3 FA SO 0 4x1 B3 Y3 C4 MUX Cout Output D A+E D=A+B+1 D AB' D AB'+ 1 D A D A+1 D A-1 S1 S0 Cin Y Microoperation Add Add with carry Subtract with borrow Subtract Transfer A Increment A Decrement A В' В'

Registers and Register Transfer . Registers are denoted by capital letters and are sometimes followed by numerals, e.g., MAR - Memory Address Register (holds addresses for the memory unit) PC Program Counter (holds the next instruction's address) IR Instruction Register (holds the instruction being executed) R1 - Register 1 (a CPU register) We can indicate individual bits by placing them in parentheses, e.g., PC(8-15), R2(5), etc.

Block Diagrams of Registers RI 7 6 5 4 3 2 1 0 Register R Showing Individual Bits 15 0 15 0 RI PC(H) Numbering of Bits Divided Into Two Parts

Register Transfer Language Instructions . Register Transfer . Simultaneous Transfer R2<-RI .Conditional Transfer (Control Function) P: R2 R1 or .Conditional, Simultaneous Transfer

Basic Symbols For Register Transfer Symbol DescriptionExamples MAR, R2 etters (andDenotes a numerals) register Parentheses Denotes a part R2(0-7), R2(L) of a register Denotes TransferR2 of information Arrow → RI Separates 2 microoperations Comma ,

Register Transfer and Hardware Every statement in Register Transfer Language implies the existence of hardware that implements the microoperation. The statement P: R2 <- R1 implies the existence of the necessary circuitry to implement the transfer as well as the mechanism to set and clear the control variable P.

Data Transfer Using the Bus o The sekect lines S,S indicaie which of four register will have its contents transferred to the bus. In general, a bus system will multiplex k registers of n bit each to produce a n-line common bus. It will require n k x 1 multiplexers. The bus is connected to the inputs of all destination registers. and will activate the load control of the selected register when it is ready to transfer data. This can bc writcn as: .R2 ←BUS, BUS ←R1 or R2 ← RI

unction Table for the Bus Register Selected 0 0 0 0

Bus System For 4 Registers 4 Common- Line So MUX 3 MUX 2 MUX 1 MUX0 D, C, B Do Co Bo D2 D, Do C2 C, Co Register D Register C Register H Register A

Arithmetic Microoperations Symbolic Designation R3R1R2 Contents of R1 plus R2 transferred to R3 R3 *-R1-R2Contents of R1 minus R2 transferred to R3 R2 ← R2 R2く . R2 .:. I 2's compl rnent contens of R2 (inegak:) R3 ← Ri +R2 + 1 | R 1 plus 2's comp. of R2 RI ← RI + 1 | Increment content of R1 by 1 RI ← RI - 1 | Decrement content of R1 by 1 Description Complement contents of R2 (1's comp.)