Question

A retaining wall is to be constructed in a normally consolidated clayey sand deposit in the figure below. Ground water table is lmbelow the bottom of the excavation. A 20 kN/m2 surcharge pressure is applied over a wide area at the ground surface. Assume the wall moves into the excavation. Consider long-tem analysis (as it is usually the more critical analysis in excavation problems). Ignore capillarity as shown 20 kPa Clayey sand T17 kNm Y-20 kNm 5 m c'-10 kPa -20 1 m A 1 m A Clayey sand Clayey sand 1. Draw Mohr Circles that show the effective stress state at points A, B and C. (Point C is far enough not to be affected by the excavation, but it is still under the surface load) 2. Calculate the depth of tension crack. On which side of the wall do tension cracks develop? 3. Caleulate and sketch the active and passive horizontal total stress distributions along depth, using Rankine earth pressure theory. 4. When unsupported, this wall will collapse. Calculate required support force, if the supports will be placed every 4 meters into the page. (Hint: The difference between the total active force and the total passive resistance will be carried by the supports -due to the horizontal force equilibrum 5. How would you modify your solution to question 4, if the owner of the project does not tolerate horizontal displacement of the wall? (Write no more than 3 sentences) DII 北京交通大学考试试题 (A卷) 学年学期: 2018-2019学年第2学期 课程名称:_数字电子技术 梁程编号:14L1850 开课学院:电子 出题教师: 学生姓名: 任课教师: 学号: 学生学院: 班级: 九 总分 t 題号 五 得分 阅卷人 Concepts (20 points). Note that descriptions on logic symbols below can be found in the appendix in the end. 1.Write out the logic expression of the circuit in Fig.1, P L Di A B- D R Fig2 -5V Fig. 2.Write out the logic expression of the circuit in Fig 2, F 3.Write out the logic expression of the circuit in Fig 3, F A & F dEN 0- -F B- EN Fig 3 Fig4 4.What is the function realized by the circuit in Fiz4 1/7 13 5. For parity circuits, with the same number of inputs, is faster (Chain structure or Tree structure). 6. Of different types of counters, counter has the highest speed (Asynchronous, Synchronous serial or Synchronous parallel). irregular signal wave forms can be transformed to square waves 7.Using (Schmitt-Trigger, Three-state Buffer, NOT gate or Transmission gate). 8. Give one way of eliminating timing hazards in combinational circuits D CP CP Fig.5 9. Suppose the initial state of the output of the circuit in Fig.5 is 0, please draw the wave form of Q. Draw it under the CP signal (Gignoring propagation delay). 10.When using CMOSS devices to drive CMOS devices, II. The logic diagram in Fig.6 consists of a PMOS transistor, a NMOS transistor, a NOT gate and a transmission gate. Analyze the logic relationship between the inputs and the output (10 points). Note that descriptions on logic symbols below can be found in the appendix in the power is consumed end. F TG Fig. 6 III. Analyze the logic diagram in Fig.7, and tell whether it has the timing hazards problem. If it has, use a method to eliminate the timing hazards problem (Draw it in the logic diagram) (10 points). Note that descriptions on logic symbols below can be found in the appendix in the end. & & Fig.7 T IV. Analyze the function of the logic diagram in Fig.8. 74LS85 is a 4-bit comparator, and 74LS283 is a 4-bit binary adder, where AyAgA,Ao is the summand, B.B,B,Be is the addend, and S,S,S,So is the sum. CI and CO are carry in and carry out, respectively (10 points). Note that descriptions on logie symbols below can be found in the appendix in the end. As A As As B B, &B 14LS85 A A A As & B 8. B 14L5283 CO Fig 3/7 V. In the logic diagram in Fig.9, F is the output. Analyze the logic function of this circuit, and give the output sequence of F (15 points). Note that descriptions on logie symbols below can be found in the appendix in the end. 741S194 1-dR PCP MA CP 0 Ms Dsn A ro C F DL Fig.9 VI. Use D flip-flops and appropriate logic gates to realize the function presented in Table 1. In Table 1, X denotes input; O denotes state variable; Q and Q denote current state; Qnel and denote next state (10 points). Q Table 1 Qoat Qn Qin 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 1 0 1 1 1 VII. Analyze the circuit in Fig. 10, and draw its state diagram (15 points). Note that deseriptions on logie symbols below can be fou in the appendix in the end. And Array Lde Or Array CP Fig. 10 VIlII. The logic diagram in Fig.11 consists of a shift register 74195 and a 4-bit D/A converter DAC. List the output voltage v in order. Here, DAC performs the digital signal to analog signal conversion. The resolution of the analog output is 0.1 volt. For example, when its input D.P-D.Dais 0000, its output is 0 volt. And, when its input DaD D,Do is 0001, its output is 0.1 volt (10 points). Note that descriptions on logic symbols below can be found in the appendix in the end. Sat pulse DAC th Fig.11 5/7 Appendix :AND gate; NAND gate, :Exclusive OR gate; NOT gate three-state AND gate with an active low enable input; are enable inputs transmission gate, the top and bottom inputs D flip-flop; NMOS transistor; Exclusive NOR gate n:PMOS transistor Function table of 74LS85 Cascading put Oatput Fos Faa Data Input Ia As Bo Fa A B A B As B 0 X 0 X A>B X x X AB x X X APB A-B 0 X AsB X A-B APB X Ay-B A-B x 0 1 AB AB X X X X 0 A-B A-B AB AB A Bo X X x Ay-B AB ABo X AB A-B ABi AB 0 1 AB A-B A-B AB ABe ABe C C Ay-By 0 X x A A-B A-B AB 0 A-B AB AB AB C Function table of 74194 Input Output CP D D M, M, D 0 0 1 Hold 1 d d, Q. 1 Qe 1 Q. Qr Qia Qher Qdart denotes the next state of state variables Qo Q, Q2 Hold 6/7 PPPP

Answer 1

Answers to finding logic expressions of the circuits

1. Waite dowm the logic eapession of the rauit A a o F R -FV Eaxplanatiem F A Both diedes OFF. ho cemee flowg through R output F= O +5 v f ence for carrd at B biases Do and current flowo through R Hence voltage almop acrogs R Output tigh D, Condactg flows through R 5--/R Curaent vottage drop acrossR F high Hence Both D, and Do Conducts flows through R Cunaent - 20 R Votage drop across R Hence F= High Loqfe eapredsionF = tm Truth Table A +B A OR B

Woite dowm the logfe epresolon far the iruit given be low -1 & CLK DFlep flop Tmverter AND gate A F AND CLK A B. output gate AND eauation of D Fllp flop eh aractesistic D. A. B. a Hence F = cruit 3. Wafte the logic enpregsion for the followimg dEN EN &C く0

A Buffer AND AND EN. AND EN F A.EN 8. EN (A+ EN)- B EN CA +EN). CEEN) F= Logic expresofon for logfc estpreofon for the followng Cu pefte doum the 4 ncuit & AB A F AD A AB. B AB B AB A AB A+AB B (AB).A +(A+.8 - A.At A-B +A. 0+

0 AB A B B.B 0 A B A B0 AD + AB AD F A XOR B A B

5) Tree structure is faster than chain structure. Because in tree structure more than one no of gates will function at a period. But in chain structure each gate will take its on gate time before getting output.

6) synchronous parallel counters has highest speed. because in asynchronous clock signal is applied to first flipflop. clock input to remaining flipflops will be output of previous inputs. But in synchronous clock inputs are same and applied at equal time to every flipflops.

7) Schmitt Trigger converts irregular waveforms into square waveforms. Actually its a comparator

8) simplify combinational logic

9)10) less power is consumed.

Inital Statt of eutput CLK Because edge taiggered D Fltpflop is at Sigmal ymbol is D flipflop outputs pulse D flip flop Clock +ve edge at evesy Hence of Clock eutput of a D D imput ext State CLK iSomnect ed to 1. - D khen O D , then D I Q 0, then D D 0 a then - o-D. DI