Question

ELEC3720-PROGRAMMABLE LOGIC DESIGN ASSIGNMENT 1. This assignment will give you an introductory experience on digital logic design asing CAD tools while reviewing some concepts Cveeed in the peevions courses This is an individual assignment This assignaient due on the Friday of week-3, at 17:00 hrs Please submit your assignment source code皿blackboard. Go to the 'Assignment" folder and then follow the Assigmerat 1.1 Sumin Poetal link In addition, you are regaired to submit a short repoet which should include the following Signed assessmeut iteem cover sboet The aniswers to the questions including sounce eode printouts The report should be dropped in the ELEC3720 drop-box located in the ground floor of the EA building before the deadline. Note that you are required to demonstrate your solution in your lab session in Week 4 PROBLEMS. 1. (5 marks) Figure 1: The cincuit for Qaestion I Consider the circuit in Figure 1 (a) Give a system verilog implementation of the schematic given in Figure b) Write the Boolean equations for the schematic given in Figure 1. Simplify the Boolean equations, e.g, by using Kagh mapUse these equations to design a testbench to test your system verilog module. Please show your caleulations clearly in the report. Note: This question is meat for yon practice System Verilog structural implementation skills. In practice we paefer to simplify the Bookan equations first and use simplified form to implement the module the System Verilog In that way we make sure that the circuit implemented uses less mber logic elements. The next excensise illustrates this. Marking Criteria:

Answer 1

Module mydesign(A,B,C,D,Y,Z); //Module is my black bok its name is mydesign in bractects I/Os are defined

Input A,B,C,D; //Inputs are assigned all of one bit

Output Y,Z; // Outputs are assigned of one bit

Wire a_bar,b_bar,c_bar,d_bar,z1,z2,z3,z4,z5; //wires are assigned to mede the internal connection which are not //directly connected to inputs ot outputs

Not a1 (A_bar,A); //Not is a primitive its defination like NOT( output,input); here ouput is A_bar input is A.

// A_bar is wire because it is not acessed directly.

Not a2 (B_bar,B);

Not a3 (C_bar,C);

Not a4 (D_bar,D); // Not is primitive gate available in verilog

And a5 (z1,A_bar,D_bar); // And is primitive gate available in verilog

And a6 (z2,B,C_bar);

And a7 (z3,A,C_bar,D);

And a8 (z4,A,B_bar,C);

And a9 (z5,A,B,C,D);

Or a9 (Y,z1,z3,z5);

Or a10 (Z,z2,z3);

endmodule

//Similarly other all other primites are defined all premitive follow the oreder of (output,input1,input2,input3...)

2.

//Verilog module.
module segment7(
   C,
   Y
  );

//Declare inputs,outputs and internal variables.
input [3:0] C; // C is a biput having buswidth of 4 specified in Question
output [6:0] Y; //Sevem segment consists of 7 LES so here bus width is 7 i.3[6:0]
reg [6:0] Y; // output is registered here

//always block for converting bcd digit into 7 segment format
  always @(C) // C is in sensitivity list i.e if any cahnges will happen in C this section will make changes in output
  begin
  case (C) //case statement different cases to display C =12 hex code - 1100
12 : seg = 7'b1001111; // for diplaying C 1 & 2 is zero and other

  //switch off 7 segment character when the bcd digit is not a decimal number.
  default : seg = 7'b1111111;
  endcase
  end
  
endmodule