Question

Consider the following function. (8 <A ri eve n of products) expression. Don't draw the gate 1131 0 diagram yet. (b) Use De Morgan's Laws or "bubble pushing" to convert the SOP expression to something that can be directly implemented with only NAND/NOR/inverter gates. (c) Now draw the schematic (logic gates) for the resulting NAND/NOR/inverter circuit.

Answer 1

F (a, b, c, d) = abcd f (a, b, c, d) = a b c d + a b c d + a b c d + a b c d + a b c d + a b c d 1 1 1 0. 1 1 0 1. 1 0 1 0. 1 0 0 0. 0 1 0 1. 0 0 0 0 f (a, b, c, d) = a b c d + a b c d + a b c d + a b c d + a b c d + a b c d 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 2 5 7 10 15 rightarrow a c d + a b d + b c d + b c d \r\n Morgan's law babble pushing for