Question

implement the following hardware synchronously in verilog

سخت افزار ضرب Start Multiplier0 = 1 Multipiero = 0 1. Test Multipliero 1a. Add multiplicand to product and place the result in Product register 2 Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit No: < 32 repetitions 32nd repetition? Multiplicand Shift left B4 bits Yes: 32 repetitions 64-bit ALU Done Nultiplier Shit right 32 bits Product Controltos! Write 64 bits

Answer 1

the following is the design code

// Code your design here
module multiplier(clk,reset,A,B,product);
input clk,reset;
input [31:0] A,B;
output reg [63:0] product;
reg [31:0] multiplicand, multiplier;
integer count;
reg state;
always@(posedge reset)
begin
multiplicand=A;
multiplier=B;
count=0;
state=0;
product=0;
end
  
always@(posedge clk)
begin
if(state==0)
begin
if(count==32)
begin
state<=1;
end
else
begin
if(multiplier == 0)
begin
multiplicand<=multiplicand << 1;
multiplier<=multiplier>>1;
end
else
begin
product<=product+multiplicand;
multiplicand<=multiplicand << 1;
multiplier<=multiplier>>1;
end
count<=count+1;
end
end
else
product<=product;
end
endmodule

// Code your testbench here
// or browse Examples
module test();
reg clk,reset;
reg [31:0] A,B;
wire [63:0] product;
  
  
multiplier m1(clk,reset,A,B,product);
  
initial
begin
A=12;B=12;
clk=0;reset=0;
#2 reset=1;
#2 reset=0;
#200 $finish;
end
  
initial
forever
#2 clk=~clk;
  
initial
begin
$dumpfile("dump.vcd");
$dumpvars(2);
end
endmodule