Question

400 MHz CPU with 5 stage execution, 1 clock Instruction fetch 1 clock Decode 0 clock...

400 MHz CPU with 5 stage execution,
1 clock Instruction fetch
1 clock Decode
0 clock data fetch
8 clock execution
0 clock write back.
A. How many clocks to complete 1 instruction?
B. How many instructions are completed in a second if not pipelined?
C. How many instructions are completed in a second if pipelined?  
D. How many instructions are completed in a second if pipelined and execution stage superscalar?

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Answer #1

A) 1+1+0+8+0= 10 clock cycle

B)400MHz = 400 Million cycles per second=400,000,000

total no. of clock cycle per instructions=4

For every 10 cycles one instruction is completed

So, in one second the total 400,000,000/10 = 40,000,000 instruction are completed if not pipelined

C) If it is pipelined then the first instruction is completed in the first 10 clock cycle, and for every next clock cycle one instruction gets completed.

So, 400,000,000-10= 399,999,990 instructions are completed.

D) If it is pipelined and execution stage superscalar then two stage per clock cycle is executed i.e. 5 cycles for one instruction and pipeline the consecutive instructions it results in

400,000,000-5= 399,999,995 instructions will be completed in a second.

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