Consider a machine, which has a clock rate of 210 MHz. The following measurements are recorded on the machine running a given set of benchmark programs. Determine the effective CPI, MIPS rate, and execution time for the machine
Instruction type | Instruction count Millions | CPI |
---|---|---|
Arithmetic and logic | 6 | 2 |
Load and store | 3 | 3 |
Branch | 2 | 6 |
Others | 4 | 3 |
Consider a machine, which has a clock rate of 210 MHz. The following measurements are recorded...
c. Performance: Company A's processor and Company B's processor are benchmarked on the same program. The CPI of the component instructions that are executed in the program are shown above for each processor. Additionally, the number of instructions of each type is provided. Company A 5 Branch CPI Load/Store CPI Arithmetic CPI 7 1 Company B 4 Branch CPI Load/Store CPI Arithmetic CPI 9 1 Program Instruction Count Branch Load/Store Arithmetic CPL 1.2x109 1.67x1010 1.5x1011 i. Assume Company A has...
Problem 1 Assume that a processor with a clock rate of 1 GHz clock runs a benchmark program w mix of instructions given in the table below. Instruction class CPI FP INT Load/Store (L/S) Branch Instruction count 50 x 106 110 x 106 50 x 106 10 x 106 By how much must the CPI of L/S instructions be improved if the program is to run two times faster?
18. We have two types of machine as follows: Processor Clock Rate (MHz)PSat CPU time (see 12 x Machine A Machine B 25 Mache A requires 12 times longer than Machine B measured in CPU time. For example, a program takes 1 second in Machine B will take 12 seconds. 1) What is the relative size of the instruction count for the program running on the two machines? 2) What is the effective CPI for the two machines?
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock rate is 3GHz, which code sequence will execute faster according to execution time? or According to MIPS? By how much? (25 pts CPI for Instructions Code from Instruction Count (billions) CPI Compiler 1 Compiler 2 9 1 3 (e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock...
A processor is designed such that the clock of the processor runs at 1 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 10 cycles Arithmetic Instructions 65% 6 cycles Branch instructions 10% 4 cycles (a) Calculate the CPI for the above benchmark. (b) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
Figure 1: each block gives the number of different types of instructionsConsider a program with the execution flow shown in Figure 1. There are in total 3 types of instructions used in this program: Type 1 (in-processor calculation): execution rate as 1 per clock cycle; Type 2 (memory access): each instruction takes 2 clock cycles for execution; Type 3 (loop control): each instruction takes 2 clock cycles for jump into the loop block or 3 clock cycles for jump to the block after...
Please Solve 1(c). itby important Q. Disc uss the features of RISC and CISC Architecture. dware implementations Mt &t M2 of the same instruction set. There are three classes F, I & N of instructions in the instruction The average CPl for the three instructi Class set. Miclock rate is 600 MHz, M2's clock cycle is 2ns. on classes on M1 & M2 are as follows: Comments Floating Point Integer Arithmetic Non-arithmetic CPI for M 5.0 2.0 2.4 CPI for...
Given a processor that runs at 1GHz with the following: Instruction-------------- Frequency --------------Cycles Load & store ----------------25% --------------------10 arithmetic instructions------ 65% --------------------6 branch instructions -----------10%-------------------- 4 1) Calculate the CPI for the above. 2) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new clock speed (in GHz)? 3) Assume only the load & stores instructions are speed up by 5 times and their frequency is increased to 50% (Arithmetic instructions...