For 4G:
Cache Capacity for data in Byte = 2^3= 8 bytes.
Tag field = 16 bit - (12+3) bit = 1 bit
Cache Line size=2^12 /16=2^8=256 bits
For 8G:
Cache Capacity=2^4=16 bytes
For 16G:
Tag field =14 bit
Offset field =3 bit
Cache capacity=2^3 =8 bytes
Cache line size=64bit/2*16=2 (words)
Index field=log2(2)=1 bit
3) For cache design with following characteristics, complete the following tables for other parameters. Consider 16-bit...
1. Cache memory (8pts) Consider adding cache to a processor-memory system design. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses. a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...
1. Cache memory (8pts) Consider adding cache to a processor-memory system desigrn. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...
Please answer all parts correctly and show your work 3- for a direct mapped cache design with a 32 bit address, the following bits of address are used to access the cache Tag Index Offset 31-10 9-5 4-0 Starting from power on, the following byte addressed cache reference are recorded. Address 0 16 132 232 160 1024 30 140 3100180 2180 d. How many blocks are replaced e. What is the hit ratio f. List final state of the cache,...
3. (12 points) Consider a cache has lines of 16 bytes and a total size of 16 kB. The main memory is 16MB and a word takes 4 bytes. For the hexadecimal main memory addresses FFF666, show the following information in hexadecimal format a. Tag and word values for associative cache b. Tag, set and word values for a two-way set-associative cache 3. (12 points) Consider a cache has lines of 16 bytes and a total size of 16 kB....
1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit address. There are four different caches a. A direct-mapped cache with block size = 16 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size=4 words d. A fully associative cache with block size = 16 words. Complete the table for each cache. Cache a Cache be Cache Cache de 16 Number of bits needed for...
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag Index Offset 31-10 9-4 3-0 How many entries does the cache have?
Consider a 32-bit microprocessor that has on-chip 16Kbyte four-way set associative cache. Assume that cache has a line size of four 32-bit words. How many number of set are there? Sketch block diagram of this cache showing its organization. Where in the cache is the word from memory location ABCDE7F4.
Consider a 64-bit computer with a simplified memory hierarchy. This hierarchy contains a single cache and an unbounded backing memory. The cache has the following characteristics: • Direct-Mapped, Write-through, Write allocate. • Cache blocks are 4 words each. • The cache has 256 sets. (a) Calculate the cache’s size in bytes. (b) Consider the following code fragment in the C programming language to be run on the described computer. Assume that: program instructions are not stored in cache, arrays are...
Question 10 (10 points) Consider a cache of 8 lines of 16 bytes each. Main memory is divided into blocks of 16 bytes each. That is, block 0 has bytes with addresses 0 through 15, and so on. Now consider a program that accesses memory in the following sequence of addresses: Loop three times: 10 through 20; 32 through 52. Once: 20 through 35. Suppose the cache is organized as direct mapped. Memory blocks 0, 8, 16 and so on...
3. (6 pts) Consider a new processor. The memory system is 32-bit byte- addressable. The on-chip cache memory is 128 KByte 4-way set-associative, with a 64 byte block size. (a) Draw a diagram showing how the cache controller will split the memory address: for each field. show its name and number of bits. (b) The design team decided to change the cache architecture to a direct mapped one. For each of the parameters in the following table, indicate the impact...