Question

1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit address. There are four different caches a. A direct-mapped cache with block size = 16 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size=4 words d. A fully associative cache with block size = 16 words. Complete the table for each cache. Cache a Cache be Cache Cache de 16 Number of bits needed for byte displacement Number of bits needed for word displacement (in block) Number of bits in tag 1 27° 28° 28 28 Number of sets in cache 2. Here is a series of addresses in hexadecimal:- 20, 3C, 28, 16, 17- Assume a LRU replacement algorithm. For cache a in problem 1, draw the cache as it would appear at the end of the series of references. Include the valid bit, dirty bit, and tag. Assume all are reads. For each address, show the contents of the block using the byte address range such as M[20-23] for the word with address 20 (if the block size is 1 word). 3. Repeat the problem above for cache b.

Answer 1

Ans for question 1(a,b,c,d)

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Ans for question 2

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Ans for question 3

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