Question

) Consider an 8-way associative 64 Kilo Byte cache with 32 byte cache lines. Assume memory...

) Consider an 8-way associative 64 Kilo Byte cache with 32 byte cache lines. Assume memory addresses are 32 bits long.

a). Show how a 32-bit address is used to access the cache (show how many bits for Tag, Index and Byte offset).

b). Calculate the total number of bits needed for this cache including tag bits, valid bits and data

c). Translate the following addresses (in hex) to cache set number, byte number and tag (i) B2FE3053hex (ii) FFFFA04Ehex (iii) FFEEA0FFhex (iv) 0B0EF3056hex

0 0
Add a comment Improve this question Transcribed image text
Answer #1

= Block size & lines =2 lined hence spits are 32 B size of line 28 Bytes = hence & bit are required for Block off on no. of s② total no. of bith need? ith n total lines = 2 linen? index bit 6 total bite = 2 Trolid bit & tay bits + Calatabit) offret bSimilarly FFFFAO AE tay S set No offaet F FEE AO FF E tt tag Set No Block . t (10) ROBO EF 3056 tay Set Block no ofset

Add a comment
Know the answer?
Add Answer to:
) Consider an 8-way associative 64 Kilo Byte cache with 32 byte cache lines. Assume memory...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Q2. Consider a four-way set associative cache with a data size of 64 KB. The CPU...

    Q2. Consider a four-way set associative cache with a data size of 64 KB. The CPU generates a 32-bit byte addressable memory address. Each memory word contains 4 bytes. The block size is 16 bytes. Show the logical partitioning of the memory address into byte offset, cache index, and tag components.

  • Assume the cache can hold 64 kB. Data are transferred between main memory and the cache...

    Assume the cache can hold 64 kB. Data are transferred between main memory and the cache in blocks of 4 bytes each. This means that the cache is organized as 16K=2^14 lines of 4 bytes each. The main memory consists of 16 MB, with each byte directly addressable by a 24-bit address (2^24 =16M). Thus, for mapping purposes, we can consider main memory to consist of 4M blocks of 4 bytes each. Please show illustrations too for all work. Part...

  • a) Suppose we have a 64 KB, direct-mapped cache with 8-word blocks. Determine how many bits...

    a) Suppose we have a 64 KB, direct-mapped cache with 8-word blocks. Determine how many bits are required for the tag, index, and offset fields for a 32-bit memory address. b) If instead, we use a 64 KB, 4-way set-associative cache with 8-word blocks, how many bits will be required for the tag, index, and offset fields for a 32-bit address? c) What type of cache is shown in problem 2? How many bits are required for this cache’s tag,...

  • Please refer the following memory system : Main memory : 64 MB Cache memory: 64 KB...

    Please refer the following memory system : Main memory : 64 MB Cache memory: 64 KB Block size of 1 KB 1. Direct Mapping Offset bits? Number of lines in cache? Line number bits? Tag size? 2. Fully Associative Mapping Offset bits? Tag size? 3. 2-way set-associative mapping Offset bits? Number of lines in cache? Set number bits? Tag size? 4. 4-way set-associative mapping Offset bits? Number of lines in cache? Set number bits? Tag size?

  • 1- A 64-bit computer system employs a 16Gbyte main memory and a 32 Kilo word cache. Determine the...

    1- A 64-bit computer system employs a 16Gbyte main memory and a 32 Kilo word cache. Determine the number of bits in each field of the memory address register (MAR) as seen by cache in the following organizations (show your calculations): Fully associative mapping with line size of 2 words. A. Direct mapping with the line size of 8 words. B. C. 4-way associated mapping with the line size of 1 words. 1- A 64-bit computer system employs a 16Gbyte...

  • Memory Hierarchy and Cache Consider a computer with byte-addressable memory. Addresses are 24-bits. The cache is...

    Memory Hierarchy and Cache Consider a computer with byte-addressable memory. Addresses are 24-bits. The cache is capable of storing a total of 64KB of data, and frames of 32 bytes, Show the format of a 24-bit memory address for: a- Direct mapped cache b- 2-way associative cache c- 4-way associative cache d- For each type of cache above, indicate where would the reference memory address 0DEFB6 map

  • Assume the following about a computer with a cache: .. The memory is byte addressable. •...

    Assume the following about a computer with a cache: .. The memory is byte addressable. • Memory accesses are to 1-byte words (not to 4-byte words). .. Addresses are 8 bits wide. .. The cache is 2-way associative cache (E=2), with a 2-byte block size (B=2) and 4 sets (5=4). • The cache contents are as shown below (V="Valid"): Set #Way #0 Way #1 V=1;Tag=0x12; Data = v=1;Tag=0x10; Data = Ox39 0x00 0x26 Ox63 V=1;Tag=0x09; Data = v=1;Tag=0x11; Data =...

  • 1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit...

    1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit address. There are four different caches a. A direct-mapped cache with block size = 16 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size=4 words d. A fully associative cache with block size = 16 words. Complete the table for each cache. Cache a Cache be Cache Cache de 16 Number of bits needed for...

  • 2. Set Associative Cache (36 pts) Given the following address access stream, please answer 2.1, 2.2...

    2. Set Associative Cache (36 pts) Given the following address access stream, please answer 2.1, 2.2 and 2.3. All the addresses are 32-bit. The sequence is shown below. Load Load Store Store Load 0x22160788 Ox09000E40 0x1265024C 0x22160484 0x1265014C 2.1 (11 pts) A 512 bytes, 2-way writeback cache. The cache line size is 64 bytes. Please calculate the number of bits used for tag, set index, and offset. Number of tag bits = Number of index bits = Number of offset...

  • Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a...

    Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT