Question

Q2. Consider a four-way set associative cache with a data size of 64 KB. The CPU generates a 32-bit byte addressable memory address. Each memory word contains 4 bytes. The block size is 16 bytes. Show the logical partitioning of the memory address into byte offset, cache index, and tag components.

Answer 1

Consider the following data: CPU generates a 32-bit byte addressable memory address Means. Physical address = 32 bit. Cache data size-64 KB-) 26 KB-) 26*210 bytes-) 216 bytes Block size = 16 bytes 24 bytes Hence, in a block a memory contains 4 bytes word Therefore, the block offset is 4 A set associative k-4 Now, we go to find out the number of lines CacheSize BlockSize Number of lines- 216 bytes 2 lines 2*bytes Hence, the number of lines is 2 2 Now, the 4-way set associative, it means every set have 4 lines Total number of lines number of lines in a set Thus, the number of sets -log 12 = log(,) = 210 2 Hence, the number of set is 10 bits Now, we have total physical address bit 32 bits

tagbit Physical address- set number block offset) 32-(10+4) -18bits Hence, the cache logical partitioning of the memory address is as given below: 32 bits Physical Address 18 bits 4bits 10 bits Set Number Tag bit Block offset