Question

please solve e & f for this question.

1. (40 points) The Corei7-6700K microprocessor has 3 cache levels about the L2 cache per core and the main memory: (more detailed information can be found at: http://www.cpu-world.com/CPUs/Core i7/Intel-Core%2017-6700.html The following is the information Memory is byte addressable Maximum memory capacity is 64 GB (G=230). Cache capacity is 256 KB (K=210) 4-way set associative is used - Block offset size is 6 bits. If CPU has generated the physical address (411234)10, what is the cache address (entry) for the block containing this address? e. f. Show the partitioning of the physical address (number of bits in each field): Index Tag Block Offset

Answer 1

f) Physical memory size = 64 GB = 2⁶*2³⁰ bytes = 2³⁶ bytes

Therefore, the physical address is of 36 bits.

Block Offset is given as 6 bits.

Therefore block size = 2⁶ bytes.

Cache capacity = 256 KB = 2⁸*2¹⁰ bytes = 2¹⁸ bytes.

Therefore, the number of blocks in the cache = 2¹⁸ / 2⁶ = 2¹²

As it is 4 way set associative so, number of sets in the cache = 2¹² / 2² = 2¹⁰.

Therefore the index field is of 10 bits.

Remaining bits = 36 - 6 - 10 = 20 bits

Therefore TAG will be of 20 bits.

TAG(20 bits)

INDEX(10 bits)

BLOCK OFFSET(6 bits)

e) Address = 411234(in decimal) = 00000000000000000110 0100011001 100010

The block containing this address will be mapped to the set 0100011001 = 281(decimal) with the TAG 00000000000000000110.

Now the number of sets before the set 281 = 281 sets [ as address starts from 0]

Now the number of blocks per set = 4 [ as 4 way set associative]

So address of the previous block in cache = 281*4 = 1124

Therefore address of this block in cache = 1125