Question

Question 6 For the following figure shows a hypothetical memory hierarchy going from a virtual address to L2 cache access. The page size is 8KB, the TLB is direct mapped with 128 entries. The L1 cache is a direct mapped 8 KB, and the L2 cache is 2MB and direct mapped. Both use 64 byte blocks. The virtual address is 64 bits and the physical address is 41 bits. For each block in the figure below, fill in the number of bits that are used for all the translations, comparisons , indices, etc. in all the places indicated. Virtual Address 64 bits Page Offet Virtual Page Number bits bits Block Offet TLB Tag compare Address TLB Index L1 Cache Index bits bits bits bits To CPU bits bits TLB Tag TLB Data L1 Cache Tag L1 Data bits bits bits L1 Tag compare Address To CPU ? bits Physical Address Block Offet L2 Cache Index L2 Tag compare Address bits bits bits To CPU L2 Cache Tag L2 Data bits bits To L1 Cache or CPU

Answer 1

Virtual addrn 64 bits Payc Siic 8K v Peye 13 no. SI bit Paye offst 13 bit 2: 128 PO.-13 bit TLB Ty Comp add TLB indem Block ofesc LI Corhe linder 7 bit 6 bit 44 bit To epu LI deta L Cahe TUB TL B Tuy 44 bit daty 6 bit 2 oits To cpU LI Tay Cumpane bits 28 cuhe /24 213 2entes -1 bit incen Phagsical celdran BO69 : 26 こんbit 41 b45 cuehe incur Blvela tup し2 addrem 2o bis 6 bit し2 し2 Ceuhe data 20 bits し2 Cache 2 2 /26 2 2 : 15 bit indlen

I hope this will help you so please give positive ratings :)))