According to its design specification, the timer circuit
delaying the closing of an elevator door is to have a capacitance
of 25.0 µF between two points A and B. When one
circuit is being constructed, the inexpensive but durable capacitor
installed between these two points is found to have capacitance
28.6 µF. To meet the specification, one additional capacitor can be
placed between the two points.
Capacitors in series add like this:
1/Cs = 1/C + 1/C ....
while capacitors in parallel add up like this:
Cp = C + C... etc.
So added caps in series lowers the the capacitance.
For (a) then it is series
b)
1/28.6 = 1/25 + 1/C2
C2 = 198.611
For (c) we need a 0.5uF capacitor to make the 25uF.
According to its design specification, the timer circuit delaying the closing of an elevator door is...
According to its design specification, the timer circuit delaying the closing of an elevator door is to have a capacitance of 35.0 μF between two points A and B. When one circuit is being constructed, the inexpensive but durable capacitor installed between these two points is found to have capacitance 38.6 μΕ To meet the specification, one additional capacitor can be placed between the two points. (a) Should it be in series or in parallel with the 38.6 μF capacitor?...
Help me solve these questions, please show work.
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summatize the following info and break them into differeng key points. write them in yojr own words
apartus
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