Question

4. Write VHDL for the below logic circuit. Simulate it for 3 test cases {abcd, s0s1} = {01 10 11 11, 01}, {11 10 00 01, 10}, {10 11 00 00, 00}

a, b, c, d are 2-bit inputs. s0, s1 are 1-bit inputs. F is 3-bit includes carry and sum.

write VHDL for the below logic circuit. Simulate it for 3 test cases {abcd, s0s1}-{01 10 11 11, 013, 111 10 00 01, 10), 110 11 00 00, 00) 4. a, b, c, d are 2-bit inputs. s0, s1 are 1-bit inputs. F is 3-bit includes carry and sum so SI

Answer 1

Truth Table of 2 bit Adder:

INPUTs				SUM		CARRY
X1	X0	Y1	Y0	S1	S0	C
0	0	0	0	0	0	0
0	0	0	1	0	1	0
0	0	1	0	1	0	0
0	0	1	1	1	1	0
0	1	0	0	0	1	0
0	1	0	1	1	0	0
0	1	1	0	1	1	0
0	1	1	1	0	0	1
1	0	0	0	1	0	0
1	0	0	1	1	1	0
1	0	1	0	0	0	1
1	0	1	1	0	1	1
1	1	0	0	1	1	0
1	1	0	1	0	0	1
1	1	1	0	0	1	1
1	1	1	1	1	0	1

vhdl codes

00 ol 10 이 0 T Yo 이 lo I yo 01

----adder

library ieee;
use ieee.std_logic_1164.all;

entity add_2bit is
   port (   x    : in std_logic_vector(1 downto 0);
       y   : in std_logic_vector(1 downto 0);
       s   : out std_logic_vector(1 downto 0);
       c   : out std_logic
   );
end add_2bit;

architecture arch of add_2bit is

begin

s(1) <= ((x(1) xor y(1)) and (not x(0) or not y(0))) or ((x(0) and y(0)) and (x(1) xnor y(1)));
s(0) <= x(0) xor y(0);
c <= (x(1) and y(1)) or (x(1) and x(0) and y(0)) or (x(0) and y(1) and y(0));

end arch;

------------------------------------------------------------------------------------------------------------------------------------------

---Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2_1 is
Port ( x, y : in STD_LOGIC_VECTOR (1 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (1 downto 0));
end mux2_1;

architecture Behavioral of mux2_1 is

begin

z <= x when (s = '0') else y when (s = '1') else "ZZ";

end Behavioral;

--------------------------------------------------------------------------------------------------------------------

----Top File

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity logic_circuit is
Port ( a, b, c, d : in STD_LOGIC_VECTOR (1 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
F : out STD_LOGIC_VECTOR (2 downto 0));
end logic_circuit;

architecture Behavioral of logic_circuit is

component add_2bit is
   port (   x    : in std_logic_vector(1 downto 0);
       y   : in std_logic_vector(1 downto 0);
       s   : out std_logic_vector(1 downto 0);
       c   : out std_logic
   );
end component;

component mux2_1 is
Port ( x, y : in STD_LOGIC_VECTOR (1 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (1 downto 0));
end component;

signal reg : std_logic_vector(2 downto 0);
signal r0, r1, r2 : std_logic_vector(1 downto 0);
signal r3 : std_logic;

begin

U0: mux2_1 port map (a, b, s(0), r0);
U1: mux2_1 port map (c, d, s(1), r1);
U2: add_2bit port map (r0, r1, r2, r3);

F <= (r3 & r2);

end Behavioral;

-------------------------------------------------------------------------------------------------------------

---Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_logic_circuit IS
END tb_logic_circuit;

ARCHITECTURE behavior OF tb_logic_circuit IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT logic_circuit
PORT(
a : IN std_logic_vector(1 downto 0);
b : IN std_logic_vector(1 downto 0);
c : IN std_logic_vector(1 downto 0);
d : IN std_logic_vector(1 downto 0);
s : IN std_logic_vector(1 downto 0);
F : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
  

--Inputs
signal a : std_logic_vector(1 downto 0) := (others => '0');
signal b : std_logic_vector(1 downto 0) := (others => '0');
signal c : std_logic_vector(1 downto 0) := (others => '0');
signal d : std_logic_vector(1 downto 0) := (others => '0');
signal s : std_logic_vector(1 downto 0) := (others => '0');

    --Outputs
signal F : std_logic_vector(2 downto 0);


BEGIN

   -- Instantiate the Unit Under Test (UUT)
uut: logic_circuit PORT MAP (
a => a,
b => b,
c => c,
d => d,
s => s,
F => F
);

-- Stimulus process
stim_proc: process
begin      
-- hold reset state for 100 ns.
wait for 100 ns;  
       a <= "01";
       b <= "10";
       c <= "11";
       d <= "11";
       s <= "01";
       wait for 20 ns;
      
       a <= "11";
       b <= "10";
       c <= "00";
       d <= "01";
       s <= "10";
       wait for 20 ns;
      
       a <= "10";
       b <= "11";
       c <= "00";
       d <= "00";
       s <= "00";
       wait for 20 ns;
  

wait;
end process;

END;
----------------------------------------------------------------------------------------------------------------------------------------

----------------Simulation

isim (P.68d)-[Default.wcfg] File EditView Simulation Window Layout Help 1.00us Instance ++ 354 ns Smulation Ob Value 100 ns 140 ns Instance and 10 tb_logic Object Name 10 10 100 010 X1: 129.854ns Default.wefg WARNING: Ism wil run n Lite mode. Please refer to the isim documentation for more information on the differences between the Lite and the Full version. This is a Lite version of ISim. Time resolution is 1ps Simulator is doing circuit initiaization process. Finished cicuit initialzation process ISim> Consol Compiaton Log Breakpoints Find in Fies Results Search Results Sim Time: 1,000,000 ps ENG 458 AM O Type here to search US 2/22/2019