Question

Large ROMs or RAMs are organized in a matrix with row and column addresses. How would you have to modify the RAM cell to allow a Row/Column addressing mode?

Answer 1

A DRAM / SRAM memory cell is a capacitor that is charged to produce a 1 or a 0. Over the years, several different structures have been used to create the memory cells on a chip.

So the combination of row select and column select can address an individual memory cell.

This is Random Access Memory because any bit is directly accessible, no matter what the address is. it goes for DRAM as well as SRAM.

The memory chip's support circuitry allows the user to read the data stored in the memory's cells, write to the memory cells, and refresh memory cells. This circuitry generally includes:

• Sense amplifiers to amplify the signal or charge detected on a memory cell.

• Address logic to select rows and columns.

• Row Address Select (RAS) and Column Address Select (CAS) logic to latch and resolve the row and column addresses and to initiate and terminate read and write operations.

• Read and write circuitry to store information in the memory's cells or read that which is stored there.

• Internal counters or registers to keep track of the refresh sequence, or to initiate refresh cycles as needed.

• Output Enable logic to prevent data from appearing at the outputs unless specifically desired.

Since DRAM memory cells are capacitors, the charge they contain can leak away over time. If the charge is lost, so is the data. To prevent this from happening, DRAMs must be refreshed -- that is, the charge on the individual memory cells must be restored periodically.

There are three ways to allow the memory cell by refreshing...

1. Using RAS Only Refresh (ROR)
2. Using CAS before RAS Refresh (CBR)
3. Self Refresh (SR)

A typical static memory chip will be wired internally as a row/column grid and will have about half of its address pins wired to control "row" and half to control "column", a typical dynamic memory chip will use one set of address pins to control both row and column.

To access dynamic memory, one must select a row address and then assert a pin called /RAS (Row Address Select).

This will both latch a row address and cause that particular row of memory locations to be read to a temporary buffer.

One may then use the address pins along with some other control pins to access that temporary buffer in a manner similar to a static RAM.

Once one is done with a row, one may should /RAS. This will cause the (possibly modified) contents of the row buffer to be copied back to the corresponding row in the array. Some time after /RAS is released, the memory chip will be ready to receive another row address and have /RAS asserted again.