3.2.1 A 10-MHz clock oscillator transitioning from 0 to 5 V with
rise/falltimes of 20 ns and a 50% duty cycle is connected to a gate
as shown in Fig. P3.2.1. A filter is connected as shown. Determine
the level of the 11th harmonic at the gate terminals. Obtain these
by using the exact expression and by using the spectral bounds.
[73.95 dBmV exact, 78.56 dBmV by interpolation] Use PSPICE to
confirm this. [4.981 mV or 73.95 dBmV]
FIGURE P3.2.1.
3.2.1 A 10-MHz clock oscillator transitioning from 0 to 5 V with rise/falltimes of 20 ns...
The answers are at the end of the question but I am not sure if they are right/I do not know how they get those numbers 3.2.1 A 10-MHz clock oscillator transitioning from 0 to 5 V with rise/falltimes of 20 ns and a 50% duty cycle is connected to a gate as shown in Fig. P3.2.1. A filter is connected as shown. Determine the level of the 11th harmonic at the gate terminals. Obtain these by using the exact...
A 5-V, 10-MHz oscillator having a rise/falltime of 10 ns and a 50% duty cycle is applied to a gate as shown in Fig. P3.2.4. Determine the value of the capacitance such that the fifth harmonic is reduced by 20 dB in the gate voltage VG(t). [63.34 pF] LClock Gate FIGURE P3.2.4