Question

4:02 00 LTE il 50% + ENEE 2586 - Lab 9_f... @ + : ENEF 356 Lab -Sequence Detector ENEE 2586 Lab #9 - Sequence Detector Purpose: The goal of this lab is to design a sequence detector using sequential logic circuits Procedure: 1. Design a sequential logic circuit to check an input stream labeled X and to produce an output Z=1 for any input sequence ending in 101 and 1001. Use the following test sequence to verify your circuits operation: X = 110100110010110 Z = 000100100010100 Make sure your circuit has a start state and the means to manually reset the flip-flops to the start state. Note that sequences may overlap. i.e., the circuit does not reset to the start state when an output 7-1 occurs. Testing your circuit will involve checking the correctness of every state and next states for all possible combinations of the input. 2. Design a sequential logic circuit to check an input stream labeled X and to produce an output 2-1 if the total number of zeros received is odd and the sequence 100 has occurred at least once. The total number of zeros received include before, during and after the sequence 100 is received. Use the following test sequence to verify your circuits operation: X = 110100110010110 Z = 000001000100001 Make sure your circuit is a Moore circuit and it has a start state and the means to manually reset the flip nops to the start state. Note that the circuit does not reset to the start state when an output 7-1 occuni. Testing your circuit will involve checking the correctness of every state and next states for all possible combinations of the input. Lab Report: The lab report should include at least the following 1. A cover page with the name and relevant lab information 2. A description of the design, including possible use of state graph, next state table and K-map for logic simplification 3. The logic circuit schematic of the design where elements such as flip-flops, any additional gates are shown 4. Simulation using MultiSim LogiSim of the design 5. Discussion of the implementation and testing results. Page 1 of 1

Please send an easy to read circuit design as well and explain how it works.

Answer 1

1.

State Diagram

- 0/0 Reset po 1/0 0% MEALY FSM

State Table

Use binary state encoding i.e. S0 = 00, S1 = 01, S2 = 10 and S3 = 11

STATE	PRESENT STATE	INPUT	NEXT STATE	OUTPUT
Q1	Q0	X	Q1+	Q0+	Z
S0	0	0	0	0	0	0
0	0	1	0	1	0
S1	0	1	0	1	0	0
0	1	1	0	1	0
S2	1	0	0	1	1	0
1	0	1	0	1	1
S3	1	1	0	0	0	0
1	1	1	0	1	1

Circuit Implementation is intended with D Flip Flops.

Hence we use K arnaugh Map technique to find excitation inputs for D Flip Flops

DI Q 1oo ol l 10 Q 00 01 11 10 o DI = Q, QoX+Q, QOX Do= x +Q, Qo Z QOX z = Q, X

Circuit

RESET 0 0 Denoi Ueno