Question

17. A computer system implements a paged virtual memory system. Assume a 16-bit virtual address space and a 24-bit physical address space. Assume that the first 6 bits of a virtual address index the page table and the rest of the bits are the page offset. A process has the following indexed page table. Index Page Table Entry (PTE) 0x3800 0x3600 0x3200 0x1000 2 3 Each page table entry qives a hexadecimal page frame addresses. Translate the following two hexadecimal VM addresses into their corresponding hexadecimal physical address. Hint: Translate the VM address to binary first. Translate the binary VM address to a binary PM address. Translate the binary PM address into hexadecimal . VM Address 0x084B is Physical Memory VM Address 0x0C78 is Physical Memory in
0 0
Add a comment Improve this question Transcribed image text
Answer #1

Index column in the page table is the page number. The page table entry in the page table contain the actual frame number(where the corresponding page located in physical memory) for that page number.

The first 6 bits(MSB) is the index to page table(nothing but page number).

The remaining 16-6 = 10 bits are offset which will be concatenated with the frame number to form the actual physical address.

Virtual memory addres in hexa decimal :0x084B

Virtual memory addres in binary: 0000 1000 0100 1011

The first 6 bits in virtual memory are 0000 10 => 2 (index number)

The page table entry(frame number) for index 2 is: 0x3200

Physical address = Frame number(only 14 bits for frame, remaining are used for flags ) + offset

= 0011 0010 0000 00 00 0100 1011

= 0x32004B(24 bits)

Virtual memory addres in hexa decimal :0x0C78

Virtual memory addres in binary: 0000 1100 0111 1000

The first 6 bits in virtual memory are 0000 11 => 3 (index number)

The page table entry(frame number) for index 3 is: 0x1000

Physical address = Frame number(only 14 bits for frame, remaining are used for flags ) + offset

= 0001 0000 0000 00 00 0111 1000

= 0x100078(24 bits)

Add a comment
Know the answer?
Add Answer to:
17. A computer system implements a paged virtual memory system. Assume a 16-bit virtual address space...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • 11. In a paged virtual memory system, can the computer 's physical memory address space be...

    11. In a paged virtual memory system, can the computer 's physical memory address space be larger than a process's virtual memory address space? Explain your answer. (Note: A computer 's "physical memory address space" is the number of bits for the frame number plus the number of bits foir the offset. A process's "virtual memory address space" is the number of bits for a page number plus the number of bits for the offset.)

  • SN 6 A system implements a paged virtual address space for each process using a one-level...

    SN 6 A system implements a paged virtual address space for each process using a one-level page table. The maximum size of virtual address space is 4KB. The page table for the running process Includes the following valid entries: Virtual Virtual page 7 - Page frame 4 Virtual Virtual page 5 - Page frame 0 Virtual Virtual page 20 - Page frame 1 Virtual Virtual page 10 - Page frame 3 Virtual Virtual page 3 - Page frame 2 The...

  • A system implements a paged virtual address space for each process using a one-level page table....

    A system implements a paged virtual address space for each process using a one-level page table. The maximum size of virtual address space is 8MB. The page table for the running process includes the following valid entries (the -> notation indicates that a virtual page maps to the givenpage frame, that is, it is located in that frame): Virtual page 2 -> Page frame4 Virtual page 4 -> Page frame 9 Virtual page 1 -> Page frame2 Virtual page 3...

  • The RISC-V 32-bit architecture supports virtual memory with 32-bit virtual addresses mapping to 32-bit physical addresse...

    The RISC-V 32-bit architecture supports virtual memory with 32-bit virtual addresses mapping to 32-bit physical addresses. The page size is 4Kbytes, and page table entries (PTEs) are 4 bytes each. Translation is performed using a 2-level page table structure. Bits 31:22 of a virtual address index the first-level page table. If the selected first-level PTE is valid, it points to a second-level page table. Bits 21:12 of the virtual address then index that second-level page table. If the selected second-level...

  • computer architecture Virtual memory 4 physice memar Assume a 64 bit machine with 40 bit addresses,...

    computer architecture Virtual memory 4 physice memar Assume a 64 bit machine with 40 bit addresses, and 16GB of actual memory. Memory blocks are 4K 1. How many bits in the virtual memory INDEX and OFFSET fields? 2. What fields do you need in a page table entry, and how many bits are needed for each? How many bytes do you need for each page table entry? (each entry is allocated in a whole number of bytes, even if there...

  • Consider the page table shown below for a system with 16-bit virtual and physical addresses and...

    Consider the page table shown below for a system with 16-bit virtual and physical addresses and with 4096-byte pages. All numbers below are given in hexadecimal. (A dash for a page frame indicates that the page is not in memory.) Page Number Physical Frame Number 0 - 1 2 2 C 3 A 4 - 5 4 6 3 7 - 8 B 9 0 How many bits are in the offset part of the address? How many hex digits...

  • Consider a virtual memory system with the following properties: 36 bit virtual byte address, 8 KB...

    Consider a virtual memory system with the following properties: 36 bit virtual byte address, 8 KB pages size, and 32 bit physical byte address. Please explain how you determined your answer. a. What is the size of main memory for this system if all addressable frames are used? b. What is the total size of the page table for each process on this processor, assuming that the valid, protection, dirty, and use bits take a total of 4 bits and...

  • A certain byte-addressable computer system has 32-bit words, a virtual address space of 4GB, and a...

    A certain byte-addressable computer system has 32-bit words, a virtual address space of 4GB, and a physical address space of 1GB. The page size for this system is 4 KB. Assume each entry in the page table is rounded up to 4 bytes. a) Compute the size of the page table in bytes. b) Assume this virtual memory system is implemented with a 4-way set associative TLB (Translation Lookaside Buffer) with a total of 256 address translations. Compute the size...

  • Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a...

    Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...

  • A computer system has a 36-bit virtual address space with a page size of 8K, and...

    A computer system has a 36-bit virtual address space with a page size of 8K, and 4 bytes per page table entry. How many pages are in the virtual address space? What is the maximum size of addressable physical memory in this system? If the average process size is 8GB, would you use a one-level, two-level, or three-level page table? Why? Compute the average size of a page table in part c above

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT