Question

QUESTION 7 A master slave flip flop behaves similarly to a clocked latch, except that the latches output can change only near the rising edge of the clock True False QUESTION 8 Assuming zero setup and hold times, clocked latches and flip-flops produce the same outputs as long as the inputs do not change while the clock is asserted True False QUESTIONS An edge-triggered D flip-flop requires more internal gates than a similar device constructed from a J-K master-slave flip flop True False QUESTION 10 The inputs to a level-sensitive latch always affect its outputs True False

Answer 1

Q7// FALSE

Explanation:Unlike the Master Slave Flipflop ,coming to clocked latch its output may changes when input changes and clock high is given....

Q8// TRUE

Explanation: Yes given statement is true...Because per suppose in a latch during the negative edge of the latch new input is asserted this will be shown on positive edge trigger ,Until unless input doesn't change while the clock is on its positive edge...

Q9//FALSE

An edge triggered D flipflop won't take much internal gates than JK flipflop for same device constructure....

Q 10// FALSE

No input to a level sensitive latch do not always effects its output becuase if we give clock low

output is not affected by inputs....
                      

Q11// TRUE

                    TRUTH TABLE FOR JK

                      J         K        Next state(Qn+1)

                     0         0             Qn(previous state)

                     0          1             0 (RESET)

                     1          0             1( SET)

                     1           1            ~Qn(Toggle)

Becuase from the truth table of JK we can see that for RESET which means (Qn+1=0) J and K are 0 and 1.

In order to SET means output 1...J must be 1 ...Coming to K if it is 0 output is SET and if it is one output (~QN) inverter of previous output...previous output is 0...Inverter of it is 1.So for getting SET from reset J must be 1 and K can be don't care....

Q12// FALSE

Given that present state is SET...from the truth table if you give J=1 and K=1 then output is inverted version of previous state....For this previous state is 1(SET) inverted output is 0( RESET).So we shouldn't give J=1&K=1.

Q13// FALSE

TRUTH TABLE FOR SR

                     S        R        Next state(Qn+1)

                     0         0             Qn(previous state)

                     0          1             0 (RESET)

                     1          0             1( SET)

                     1           1            Not allowed

Given presently RS is in SET state in order to RESET S=0 &R=1 but given that R=0 & S=1 which is false....

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