Question

by using vhdl, Build a counter to count up from 0 to 9, then repeat, using D flip-flops.

Answer 1

State Table:

PRESENT STATE				NEXT STATE
Q3	Q2	Q1	Q0	Q3+	Q2+	Q1+	Q0+
0	0	0	0	0	0	0	1
0	0	0	1	0	0	1	0
0	0	1	0	0	0	1	1
0	0	1	1	0	1	0	0
0	1	0	0	0	1	0	1
0	1	0	1	0	1	1	0
0	1	1	0	0	1	1	1
0	1	1	1	1	0	0	0
1	0	0	0	1	0	0	1
1	0	0	1	0	0	0	0
1	0	1	0	X	X	X	X
1	0	1	1	X	X	X	X
1	1	0	0	X	X	X	X
1	1	0	1	X	X	X	X
1	1	1	0	X	X	X	X
1	1	1	1	X	X	X	X

K Map Simplification for D Flip Flop Inputs

--VHDL code of D Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity dff is
   port (   clock   : in std_logic;
       reset   : in std_logic;
       din   : in std_logic;
       Q   : out std_logic
   );
end dff;

architecture arch of dff is

begin

process (clock, reset)

begin

   if (reset = '1') then
       Q <= '0';
   else
       if rising_edge(clock) then
           Q <= din;
       end if;
   end if;

end process;

end arch;

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---Top File

library ieee;
use ieee.std_logic_1164.all;

entity bcd_counter is
   port (   clock   : in std_logic;
       reset   : in std_logic;
       Q   : out std_logic_vector (3 downto 0)
   );
end bcd_counter;

architecture arch of bcd_counter is

component dff is
   port (   clock   : in std_logic;
       reset   : in std_logic;
       din   : in std_logic;
       Q   : out std_logic
   );
end component;

signal Q0, Q1, Q2, Q3, D0, D1, D2, D3 : std_logic;

begin

D0 <= not Q0;
D1 <= (not Q3 and not Q1 and Q0) or (Q1 and not Q0);
D2 <= (Q2 and not Q1) or (Q2 and not Q0) or (not Q2 and Q1 and Q0);
D3 <= (Q3 and not Q0) or (Q2 and Q1 and Q0);

UUT0: dff port map (clock, reset, D0, Q0);
UUT1: dff port map (clock, reset, D1, Q1);
UUT2: dff port map (clock, reset, D2, Q2);
UUT3: dff port map (clock, reset, D3, Q3);

Q <= (Q3 & Q2 & Q1 & Q0);

end arch;

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