Question

Design a 4-bit register using four J-K flip-flops (D4, D3, D2, and D1) with the following behaviour.

There are two control inputs, M (mode) and L (load).

When L and M are both high, data is loaded in parallel from the data inputs A4, A3, A2, and A1.

When M is high and L is low, there is a circular left shift of the data in the register.

If you can explain the work, that would be great. Really struggling with register design using flip flops.

When M and L are both low, the register is left unchanged.

When M is low and L is high, the contents of the register are inverted.

Give a design for this 4-bit register using J-K flip-flops, and whatever other hardware you need.

If you can explain the work you are doing, that would be great. Really struggling with register design using flip-flops.

Answer 1

explanation and basic hardware tips for design:

1: D-type flip flops are generally used in designing register since nextstate value is the same as the inputs.

2: T-type flip flops are generally used in counter.

using the above even if we are required to perform an operation using another flip flop we will know what the current flip flop we have should perform like.

here we want a Register logic design

hence as discussed above the flip flop generally used for these type of sequential circuits are D-flip flops

we have J-k flip flop (so from logic we see that we need this j-k flip flop to work as D-flip/flop)

how?

convert j-k flop to d

truth table for j-k

j k q qbar

00 (previous value)

01 0

10 1

11 (previous value)'

now here we see:

when here we see if j is connected to an input D and k is connected to the negation of D(i,e D')

then we will convert the j-k flip flop to D. since then is d=0 then j=0 and k=1 (hence q=0)

when D=1 then j=1 and k=0 hence q=1(following d-flip flop nextstate table logic)

now the second part of the design is input selection to these newly crated D flip flop for the required logic

the selection needs to be based on two inputs and the output is a single bit depending on the selection inputs

this logic can be performed by a multiplexer:

since we have two selection bit hence we will use 4:1 multiplexer:

with selection input as Mode and LOAD(M and L respectively)

when M=0 and L=0

the register value doesn't need to change hence if we connection 00 of mux for the output of the current flip flop the value will stay as it is.

when M=0 and L=1 the contents needs to be inverted:

hence if we connect the 01 input of multiplexer to the Qbar of the current state the output can be achieved

when m=1 and L=0 this circuit should perform circular left shift:

to achieve this if we connect the next state output to the current state(i,e the output of the right adjacent flip flop to the current 1 then it will be a left shift)hence connection right adjacent flip flop output to 10 input of mux

when M=1 and L=1 parallel load connect A4toA1 to the MSB-LSB mux on 11 of mux hence designing:

now connection the mux to the input of all the flip flop created above making the register design as shown: