Question

Design an up/down counter with four states (0, 1, 2, 3) using clocked J-K flip-flops. A control signal x is used as follows:
0 0
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Answer #1

1 & 3.

JK EXCITATION TABLE

PRESENT STATE

NEXT STATE

INPUT

Q

Q+

J

K

0

0

0

X

0

1

1

X

1

0

X

1

1

1

X

0

STATE TABLE

PRESENT STATE

INPUT

NEXT STATE

JK FLIP FLOP EXCITATION INPUTs

X

Q1

Q0

Q1+

Q0+

J1

K1

J0

K0

0

0

0

0

1

0

X

1

X

0

0

1

1

0

1

X

X

1

0

1

0

1

1

X

0

1

X

0

1

1

0

0

X

1

X

1

1

0

0

1

1

1

X

1

X

1

0

1

0

0

0

X

X

1

1

1

0

0

1

X

1

1

X

1

1

1

1

0

X

0

X

1

2.

STATE ENCODING BINARY So X SO = 00 X SI = 0 ! S2 IO X X X S2 STATE DIAGRAM x 50QIRO 00 10 11 10 00 01 11 X|X XX XX X X KI = X0+XQo Kl= X RO JI XQO+Xo JlE XQo QIRD 00 O1 11 10 01 1 X 1 X J X JO= Ko = 15.

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