A microprocessor has a decrement memory direct instruction, which subtracts 1 from the value in a...
A microprocessor has a decrement memory direct instruction,
which subtracts 1 from
the value in a memory location. The instruction has five stages:
fetch opcode (two bus
clock cycles), fetch operand address (five cycles), fetch operand
(five cycles), subtract
1 from operand (four cycles), and store operand (two cycles).
a. By what amount (in percent) will the duration of the instruction
increase if we have
to insert one bus wait state in each memory read and memory write
operation?
b. Repeat assuming that the decrement operation takes 8 cycles
instead of 4 cycles.
Homework Answers
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A microprocessor has a decrement memory direct instruction,
which subtracts 1 from
the value in a...
Exercise 1. What is the size of the memory for the microprocessor if it has 24-bit...
Exercise 1. What is the size of the memory for the microprocessor if it has 24-bit address lines (bus)? Furthermore, give the starting address and the last address of the memory. 2. List the operation modes of the ARM Cortex-M3. 3. What is the function of register R13? Register R14? Register R15? 4. On an ARM Cortex-M3, in any given mode, how many registers does a programmer see at one time? 5. Which bits of the ARM Cortex-M3 status registers...
Consider a microprocessor that has a memory read timing as shown in Figure 3.18. After some...
Consider a microprocessor that has a memory read timing as shown in Figure 3.18. After some analysis, a designer determines that the memory falls short of providing read data on time by about 180 ns. a. How many wait states (clock cycles) need to be inserted for proper system opera- tion if the bus clocking rate is 8 MHz? b. To enforce the wait states, a Ready status line is employed. Once the processor has issued a Read command, it...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requir...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requires three micro- operations to complete. Also, assume that the control memory is N bits wide (i.e., control field bits + address selection field bits + address-one bits + address-two bits N bits). The control field bits are 15 and there are 15 flags to be monitored. i. How many...
1. Cache memory (8pts) Consider adding cache to a processor-memory system design. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it take...
1. Cache memory (8pts) Consider adding cache to a processor-memory system design. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses. a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...
1. (10 points) Suppose you have a load-store computer with the following instruction mix Operation Frequency...
1. (10 points) Suppose you have a load-store computer with the following instruction mix Operation Frequency Number of clock cycles ALU ops Loads Stores Branches 40 % 20 % 18% 22 % 4 4 The ALU ops (arithmetic logic unit ops) typically use operands in CPU registers and hence they take fewer clock cycles to execute. However, if you want to add a memory operand to a CPU register, then you would have to explicitly load it into a CPU...
1. Cache memory (8pts) Consider adding cache to a processor-memory system desigrn. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes o...
1. Cache memory (8pts) Consider adding cache to a processor-memory system desigrn. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...
Instruction set architecture R: register X, Y, Op1, Op2: Operand Quantity: constant value EA: Effective memory...
Instruction set architecture R: register X, Y, Op1, Op2: Operand Quantity: constant value EA: Effective memory address Opcode Operation Name MOV X Y XCH Opl, Op2 ADD X, Y SUB X, Y SAL Op. Quantity SAR Op. Quantity SHR Op Quantity AND X, Y OR X. Y XOR X, Y NOT X LOAD RA LOAD R. (A) STORERA STORE R. (A) Description Move data from Y to X Exchange Opl with Op2 X=X+Y X=Y-X Shift Arithmetic Left on Op for...
Instruction set architecture R: register X, Y, Opl, Op2: Operand Quantity: constant value EA: Effective memory address Opcode Operation Name MOV X, Y XCH Opl, Op2 ADD X, Y SUB X,Y SAL Op, Quantity...
Instruction set architecture R: register X, Y, Opl, Op2: Operand Quantity: constant value EA: Effective memory address Opcode Operation Name MOV X, Y XCH Opl, Op2 ADD X, Y SUB X,Y SAL Op, Quantity SAR Op, Quantity Shift Arithmetic Right on Op for Quantity SHR Op Quanti AND X, Y OR X, Y XOR X, Y NOT X LOADR, A LOAD R, (A STORE R, A STORE R, (A Description Move data from Y to X Exchange Op1 with Op2...
Computer Architecture The format of this document is as follows: First, I give a practice problem...
Computer Architecture
The format of this document is as follows: First, I give
a practice problem for which the solution is also provided. In bold
italic font, I slightly modify the problem for your
homework.
3) The 4-Stage Pipeline below suffers from the memory access
resource conflict as shown below (instruction i and i+2 want to
access memory at the same time and i+2 needs to be denied, so it
waits for the next cycle; in the next cycle it...
[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment"...
[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits,...
Exercise 1. What is the size of the memory for the microprocessor if it has 24-bit address lines (bus)? Furthermore, give the starting address and the last address of the memory. 2. List the operation modes of the ARM Cortex-M3. 3. What is the function of register R13? Register R14? Register R15? 4. On an ARM Cortex-M3, in any given mode, how many registers does a programmer see at one time? 5. Which bits of the ARM Cortex-M3 status registers...
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requires three micro- operations to complete. Also, assume that the control memory is N bits wide (i.e., control field bits + address selection field bits + address-one bits + address-two bits N bits). The control field bits are 15 and there are 15 flags to be monitored. i. How many...
1. Cache memory (8pts) Consider adding cache to a processor-memory system design. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses. a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...
1. (10 points) Suppose you have a load-store computer with the following instruction mix Operation Frequency Number of clock cycles ALU ops Loads Stores Branches 40 % 20 % 18% 22 % 4 4 The ALU ops (arithmetic logic unit ops) typically use operands in CPU registers and hence they take fewer clock cycles to execute. However, if you want to add a memory operand to a CPU register, then you would have to explicitly load it into a CPU...
1. Cache memory (8pts) Consider adding cache to a processor-memory system desigrn. The microprocessor without cache needs 12 clock cycles to read a 16-bit word from the memory. With cache, it takes only 4 clock cycles if the data happens to be in the cache and a total 20 clock cycles including the cache misses a. What is the performance ratio of the cache system to the non-cache system given a hit rate of 80%? b. For what hit rate...
Instruction set architecture R: register X, Y, Op1, Op2: Operand Quantity: constant value EA: Effective memory address Opcode Operation Name MOV X Y XCH Opl, Op2 ADD X, Y SUB X, Y SAL Op. Quantity SAR Op. Quantity SHR Op Quantity AND X, Y OR X. Y XOR X, Y NOT X LOAD RA LOAD R. (A) STORERA STORE R. (A) Description Move data from Y to X Exchange Opl with Op2 X=X+Y X=Y-X Shift Arithmetic Left on Op for...
Instruction set architecture R: register X, Y, Opl, Op2: Operand Quantity: constant value EA: Effective memory address Opcode Operation Name MOV X, Y XCH Opl, Op2 ADD X, Y SUB X,Y SAL Op, Quantity SAR Op, Quantity Shift Arithmetic Right on Op for Quantity SHR Op Quanti AND X, Y OR X, Y XOR X, Y NOT X LOADR, A LOAD R, (A STORE R, A STORE R, (A Description Move data from Y to X Exchange Op1 with Op2...
Computer Architecture
The format of this document is as follows: First, I give
a practice problem for which the solution is also provided. In bold
italic font, I slightly modify the problem for your
homework.
3) The 4-Stage Pipeline below suffers from the memory access
resource conflict as shown below (instruction i and i+2 want to
access memory at the same time and i+2 needs to be denied, so it
waits for the next cycle; in the next cycle it...
[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits,...
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