Consider a microprocessor that has a memory read timing as shown in Figure 3.18. After some...
Consider a microprocessor that has a memory read timing as shown
in Figure 3.18.
After some analysis, a designer determines that the memory falls
short of providing
read data on time by about 180 ns.
a. How many wait states (clock cycles) need to be inserted for
proper system opera-
tion if the bus clocking rate is 8 MHz?
b. To enforce the wait states, a Ready status line is employed.
Once the processor
has issued a Read command, it must wait until the Ready line is
asserted before
attempting to read data. At what time interval must we keep the
Ready line low in
order to force the processor to insert the required number of wait
states?
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