Question

1. Write a Verilog module and testbench for a 3:1 multiplexer that implements the following function. You can use “case”, “if” or “assign” statements. Grades will be agnostic of your style of implementation (you can choose any of these three styles) and only on the correct functionality.

Y = S0’S1’D0 + S0S1’D1+ S1D2

Here, S0 and S1 are the two select signals and D0, D1 and D2 are the three data signals.

2. What does the following snippet of Verilog code do? Can you name the functionality that’s being represented by this? Rewrite the same functionality using case statements.

always @(A)

begin

Test=8’b00000001;

Y=3’bx;

for (N=0; N< 8; N=N+1)

begin

if(A==Test)

Y=N;

Test=Test<<1;

                                                end

                        end

Answer 1

1.Verilog code:

module mod(s0,s1,d0,d1,d2,y);
input s0,s1,d0,d1,d2;
output reg y;

always@(s0,s1)
begin

if(s1==1)
y=d2;
else if (s0==0&&s1==0)
y=d0;
else if(s0==0&&s1==1)
y=d1;

end
endmodule

module tb;
reg rs0,rs1,rd0,rd1,rd2;
wire wy;

mod m1(rs0,rs1,rd0,rd1,rd2,wy);

initial
begin
rs0=0;
rs1=0;
rd0=1;
#5 $display("s0=0 and s1=0 then y->%d",wy);
rs0=1;
rs1=0;
rd1=1;
#5 $display("s0=1 and s1=0 then y->%d",wy);
rs0=1;
rs1=1;
rd2=1;
#5 $display("s1=1 then y->%d",wy);
rs0=0;
rs1=1;
rd2=1;
#5 $display("s1=1 then y->%d",wy);
end
endmodule

Output:

2) given verilog code acting as 8*3 encoder

Vrilog cod using case:

module mod(a,y);
input[7:0] a;
output reg[3:0] y;
always@(a)
begin
case(a)
8'b00000001: y=0;
8'b00000010: y=1;
8'b00000100: y=2;
8'b00001000: y=3;
8'b00010000: y=4;
8'b00100000: y=5;
8'b01000000: y=6;
8'b10000000: y=7;
endcase
end
endmodule

module tb;
reg[7:0] ra;
wire[3:0] wy;

mod ma(ra,wy);

initial
begin
ra=8'b00000001;
#5 $display("%b",wy);
ra=8'b00000010;
#5 $display("%b",wy);
end
endmodule

Output: