3. Now let’s look at the Verilog implementation of the arbiter state machine. [Normally we would include an always block...
3. Now let’s look at the Verilog implementation of the arbiter state machine. [Normally we would include an always block for the state update but we’re not going to bother with that here.]
(a) Define the module interface and the state variables you will use. Also use a parameter statement so that you can use labels for your states. Remember to define the output signals as type reg, since you will be assigning to them inside the case statement, which is inside of an always block.
(b) Now write an always block that includes a case statement for determining both the next state transitions and the output value. Be careful to use begin/end statements where necessary.
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