Question

1. Let's implement the traffic light controller from the previous assignment in Verilog, working with the following state and module interface definition: diagram car 0 car: 1 D/MR 1SY- car 0 C/MR-1,SG module trafficController (car, clock, MG,MY,MR,SG,SY,SR) input car,clock; output MG,MY,MR,SG,SY,SR; (a) Write a parameter definition for the state encodings. But let's define them as 1-hot encoded states rather than using fully encoded state values. (b) Define two reg variables to keep track of your current state and next state, and write an always block that performs the state update on every rising edge of the clock. (c) Write an always block using a case statement to define your next state logic. Make sure to add a default case that will cause the machine to go to state A if by chance the flops are ever a value other than one of our 1-hot encodings (this could happen when the circuit is first powered on). (d) Write assign statements for each of the 6 outputs, as a function of the current state. Note that individual bits of your current state variable can be used for this.

Answer 1

module trafficController (car, clock, MG, MY, MR, SG, SY, SR);

input car, clock;

output MG, MY, MR, SG, SY, SR;

parameter A = 4'b0001, B = 4'b0010, C = 4'b0100, D = 4'b1000;

reg [3:0] current_state, next_state;

always @(posedge clock)

   current_state    <= next_state;

always @(current_state, car)

begin

   case (current_state)

           A :    if (car)
                   next_state <= B;
               else
                   next_state <= A;

           B :    next_state <= C;
          
           C :    if (~car)
                   next_state <= D;
               else
                   next_state <= C;

           D :    next_state <= A;

       default   :    next_state <= A;

   endcase

end

assign MG = (current_state == A) ? 1'b1 : 1'b0;
assign SR = (current_state == A | current_state == B) ? 1'b1 : 1'b0;
assign MY = (current_state == B) ? 1'b1 : 1'b0;
assign MR = (current_state == C | current_state == D) ? 1'b1 : 1'b0;
assign SG = (current_state == C) ? 1'b1 : 1'b0;
assign SY = (current_state == D) ? 1'b1 : 1'b0;

endmodule

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