The results of the SPEC CPU2006 bzip2 benchmark running on an AMD Barcelona has an instruction count of 2.389E12, an execution time of 750 s, and a reference time of 9650 s.
a. Find the CPI if the clock cycle time is 0.333 ns.
b. Find the SPEC ratio.
The results of the SPEC CPU2006 bzip2 benchmark running on an AMD Barcelona has an instruction...
The following table shows results for SPEC CPU2006 benchmark program bzip2 running on an AMD Barcelona Name | Intr. Count x 10° | Execution Time (seconds) | Reference Time (seconds) 820 3120 9650 bzip2 1.111 [5] <1.7> Find the CPI if the clock cycle time is 0.250 ns. 1.11.2 [5] <1.7> Find the SPECratio. 1.11.3 [5] <1.7> Find the increase in CPU time if the number of instructions of the benchmark is increased by 15% without affecting the CPI. 1.114...
Assume that for a program, compiler A results in a dynamic instruction count of 8.0E8 and has an execution time of 2.4 s, while compiler B results in a dynamic instruction count of 1.25E9 and an execution time of 1.8 s. a. [10] Find the average CPI for each program given that the processor has a clock cycle time of 2 ns. b. [10] Assume the compiled programs run on two different processors. If the execution times on the two...
Given the following calculate the SPECratio Instruction count= 2.389*1012 Execution time = 750 seconds Reference time = 9650 seconds Clock Cycle= .333 nanoseconds
Problem 3. (25 pts.) Compilers can have a profound impact on the performance of an application. Assume that for a program, compiler A results in a dynamic instruction count of 1 billion instructions and has an execution time of 1.1 seconds, while compiler B results in a dynamic instruction count of 1.2 billion instructions and an execution time of 1.5 seconds. A) Find the average CPI for each program given that the processor has a clock cycle time of 1...
Consider a machine, which has a clock rate of 210 MHz. The following measurements are recorded on the machine running a given set of benchmark programs. Determine the effective CPI, MIPS rate, and execution time for the machine Instruction type Instruction count Millions CPI Arithmetic and logic 6 2 Load and store 3 3 Branch 2 6 Others 4 3
Compilers can have a profound impact on the performance of an application. Assume that for a program, compiler A results in an instruction count of 1.0E9 and has an execution time of 1.1s, and compiler B results in an instruction count of 1.2E9 and 1.5s a. Find the average CPI for both compilers assuming a clock cycle time of 1ns. b. Another Compiler C creates for the same code on 6.0E8 instructions, and has an average CPI of 1.1. What...
Compller A Compler B Execution Ti Execution Time No. Instructions meNo. Instructions b. 1.9 s 1.60E+09 1.30E+09 2.1 s 1.71 [5] <1.4> For the same program, two different compilers are used. The table above shows the execution time of the two different compiled programs. Find the average CPI for each program given that the processor has a clock cycle time of 1 ns. 1.7.2 [5] <1.4> Assume the compiled programs run on two different processors If the execution times on...
A processor is designed such that the clock of the processor runs at 1 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 10 cycles Arithmetic Instructions 65% 6 cycles Branch instructions 10% 4 cycles (a) Calculate the CPI for the above benchmark. (b) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new...
About computer architecture and organization. Please solve those questions Thank you 2. A certain program has the following instruction classes, CPIs, and mixtures: Instruction Type CPI ratio 1.5 .40 2.1 .35 3 a. What is the average CPI for this processor? b. You have the following options: • Option 1: Reduce the CPI of instruction type B to 1.8 • Option 2: Reduce the CPI of instruction type C to 2.5 Which option would you choose and why? 3. Consider...
A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9 cycles to execute. The manufacturer has decided to design a pipelined version of this processor. For this purpose, the instruction cycle has been divided into five stages with the following latencies: Stage 1 – 2.0 ns,Stage 2 – 1.5 ns, Stage 3 – 1.0 ns, Stage 4 – 2.6 ns, Stage 5 – 1.9 ns. Each stage will require an extra 0.4 ns for...