1. 2-way Set Associative Cache Memory
Consider a hypothetical machine with 1K words of cache memory. They
are in
two-way set associative organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 9ns, the time to transfer the first word from main memory to cache is 50ns, while subsequent words require 10ns/word.
Consider the following read pattern (in blocks of 128 words, and block id starts from 0):
1 2 3 5 6 2 3 4 9 10 11 6 3 6 1 7 8 4 5 9 11 1 2 4 5 12 13 14 15 13 14
and assume each block contains an average of 48 references.
(a) What is the cache miss penalty (i.e., time to transfer one block of data from main memory to cache memory)?
a) Cache miss penalty:
Number of words in a cache block size = 128 words
Time to transfer the first word from main memory to cache in case of a miss = 50 ns
Time to transfer rest 127 words = 10*127 = 1270 ns
Therefore, time to transfer one block of data from main memory to cache memory( cache miss penalty ) = 1270 + 50 = 1320 ns.
1. 2-way Set Associative Cache Memory Consider a hypothetical machine with 1K words of cache memo...
Consider a hypothetical machine with 1K words of cache memory. They are iin direct-mapped organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 8ns, the time to transfer the first word from main memory to cache is 50ns, while subsequent words require 10ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 1 2 3 5 6 2 3 4 9 10 11 6...
Consider a hypothetical machine with 1K words of cache memory. They are iin direct-mapped organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 8ns, the time to transfer the first word from main memory to cache is 50ns, while subsequent words require 10ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 1 2 3 5 6 2 3 4 9 10 11 6...
Suppose a computer using set associative cache has 216 words of main memory and a cache of 32 blocks, and each cache block contains 8 words. 3. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields? If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?...
A 2-way set associative cache consists of four sets 0, 1, 2, 3. The main memory is word addressable (i.e. treat the memory as an array of words indexed by the address). It contains 2048 blocks 0 through 2047, and each block has eight words. (a) How many bits are needed to address the main memory? (b) Show how a main memory address will be translated into a tag, a set number, and an offset within a block. Illustrate this...
Consider a memory hierarchy using one of the three organization for main memory shown in a figure below. Assume that the cache block size is 32 words, That the width of organization b is 4 words, and that the number of banks in organization c is 2. If the main memory latency for a new access is 10 cycles, sending address time is 1 cycle and the transfer time is 1 cycle, What are the miss penalties for each of...
Consider a 32-bit microprocessor that has on-chip 16Kbyte four-way set associative cache. Assume that cache has a line size of four 32-bit words. How many number of set are there? Sketch block diagram of this cache showing its organization. Where in the cache is the word from memory location ABCDE7F4.
Make an assumption that your cache is either: Fully associative Direct mapped Two-way set-associative Four-way set-associative determine: the size of the Tag and Word for Associative cache; OR the size of the Tag, Line, and Word for Direct-Mapped Cache ; Or the size of Tag, Set, and Word for K-Way Set-Associative Cache. You may make any assumptions necessary including the number of Words in each block (recommend 2 or 4 or 8)
Set-Associative Cache. Memory is byte addressable. Fill in the missing fields based upon the properties of a set-associative cache. Click on "Select" to access the list of possible answers. Set Block Size Number of Tag Bits Select] Select] Main Memory Size Cache Size 256 B 1) 128 KiB 16 KiB 2) 32 GiB 32 KiB 1 KiB 3) [Select ] 512 KiB 1 KiB [Select ] 10 16 GiB 4 KiB Select ] I Select ] 5) 10 64 MiB...
Consider a 2-way set associative cache consisting of 8 blocks total of byte-addressable memory with 4 bytes per block. Assume that the cache is initially empty. Given the following address sequence, fill in the table below. Time Access Tag Set Offset 3 10010001 11001001 10110110 10101011 10110010
6. A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. a. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b. Compute the hit ratio for a program that loops 5 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction.