Question

Consider a hypothetical machine with 1K words of cache memory. They are iin direct-mapped organiz...

Consider a hypothetical machine with 1K words of cache memory. They are iin direct-mapped organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 8ns, the time to transfer the first word from main memory to cache is 50ns, while subsequent words require 10ns/word.

Consider the following read pattern (in blocks of 128 words, and block id starts from 0):

    1 2 3 5 6 2 3 4 9 10 11 6 3 6 1 7 8 4 5 9 11 1 2 4 5 12 13 14 15
    13 14

and assume each block contains an average of 48 references.

  1. (b) Write down the content of the cache memory (for all the blocks) at the end of the memory references, assuming that the cache is empty at the beginning.

0 0
Add a comment Improve this question Transcribed image text
Answer #1

seb 2.

Add a comment
Know the answer?
Add Answer to:
Consider a hypothetical machine with 1K words of cache memory. They are iin direct-mapped organiz...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Consider a hypothetical machine with 1K words of cache memory. They are iin direct-mapped organiz...

    Consider a hypothetical machine with 1K words of cache memory. They are iin direct-mapped organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 8ns, the time to transfer the first word from main memory to cache is 50ns, while subsequent words require 10ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 1 2 3 5 6 2 3 4 9 10 11 6...

  • 1. 2-way Set Associative Cache Memory Consider a hypothetical machine with 1K words of cache memo...

    1. 2-way Set Associative Cache Memory Consider a hypothetical machine with 1K words of cache memory. They are in two-way set associative organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 9ns, the time to transfer the first word from main memory to cache is 50ns, while subsequent words require 10ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 1 2 3 5...

  • For a direct-mapped cache memory, the following data is given.                    Main memory              &nb

    For a direct-mapped cache memory, the following data is given.                    Main memory                                       Cache memory            Size = 64KB                                               Size = 128B           Block size = 8Bytes                                    Block size = 4Bytes Calculate the following: Number of blocks created in main memory. Number of blocks created in cache memory. The distribution of the address fields in the system. Q5. For a direct-mapped cache memory, the following data is given. Main memory Cache memory Size...

  • 6. a) Consider a direct mapped cache with 10 blocks of 10 words each. Suppose main...

    6. a) Consider a direct mapped cache with 10 blocks of 10 words each. Suppose main memory is 1000 words. For each memory address below say what cache block it maps to, what is the offset, and what is the tag. 934, 666, 348, 522

  • A direct-mapped cache has 4 blocks and each block holds four bytes of data. The memory...

    A direct-mapped cache has 4 blocks and each block holds four bytes of data. The memory system is byte-addressable. Determine if each of the memory references below is a hit (H) or miss (M). You assume the cache is initially empty and memory references are given in decimal. Reference 27 0 13 24 50 24 36 14 48 45 47 48 H/M?

  • Consider a memory hierarchy using one of the three organization for main memory shown in a...

    Consider a memory hierarchy using one of the three organization for main memory shown in a figure below. Assume that the cache block size is 32 words, That the width of organization b is 4 words, and that the number of banks in organization c is 2. If the main memory latency for a new access is 10 cycles, sending address time is 1 cycle and the transfer time is 1 cycle, What are the miss penalties for each of...

  • Using the sequences of 32-bit memory read references, given as word addresses in the following table:...

    Using the sequences of 32-bit memory read references, given as word addresses in the following table: 6 214 175 214 6 84 65 174 64 105 85 215 For each of these read accesses, identify the binary address, the tag, the index, and whether it experiences a hit or a miss, for each of the following cache configurations. Assume the cache is initially empty. A direct-mapped cache with 16 one-word blocks. A direct-mapped cache with two-word blocks and a total...

  • A direct-mapped cache has 4 blocks and each block holds four bytes of data. The memory...

    A direct-mapped cache has 4 blocks and each block holds four bytes of data. The memory system is byte-addressable. Determine if each of the memory references below is a hit (H) or miss (M). You assume the cache is initially empty and memory references are given in decimal. 12 21 13 32 27 23 34 19 34 23 36 39 REFE RENC E H/M2 I

  • 3) Direct-Mapped Cache Determine the Cache line holding an address EEL 3801 UCF Given: An 8-bit...

    3) Direct-Mapped Cache Determine the Cache line holding an address EEL 3801 UCF Given: An 8-bit computer system with 4 MB of main memory. It has a 16K-words direct-mapped cache with a block size of 16 Bytes. Sought: Calculate the cache line number when Byte address 5678ten from main memory is mapped to cache. Consider that numbering of main memory blocks and cache lines starts from zero. Express your answer in hexadecimal. It is required to show ALL incremental steps...

  • Given: An 8-bit computer system with 4 MB of main memory. It has a 16K-words direct-mapped...

    Given: An 8-bit computer system with 4 MB of main memory. It has a 16K-words direct-mapped cache with a block size of 16 Bytes. Sought: Calculate the cache line number when Byte address2271len from main memory is mapped to cache. Consider that numbering of main memory blocks and cache lines starts from zero. Express your answer in hexadecimal. It is required to show ALL incremental steps of the solution.

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT