Question

IIOnTg EXcitise 0., synthesize your Vrmux4in18b cc module as well as 6.46 Cohtmu the original in Program 6-17, targeting your favorite FPGA. Determine how many LUTs are required in each of the two realizations, and explain the cause of the difference, if any rite a Verilog module Vrabcdemux for a customized multiplexer with five 8-bit nput buses A, B, C, D, and E, selecting one of the buses to drive a 8-bit output bus T according to Table X6.47. Synthesize the module for your favorite FPGA and determine how many internal resources it uses. S2 S1 SO Input to Select 0 Table X6.47 0 0

6.47 using verilog

Answer 1

module Vrabcdemux (out, A, B,C, D,E, S2, 51, 50) input [7:01A, B, C,D,E: // input 8-bit input S2,S1, s0; output [7:0] out; //output of 8 bit reg [7:0]out; always (S2 or Sl1 or S0 or A or B or C or D or E) case ((S2,S1, S0 //string concatenation //control signals 3'b000: out A; 3'b0ol: out-B; 3"b0l0: out-B 3'boll: out-C; 3 bl00: out-C; 3'bll0: out-E; 3"blll: out-A; endcase endmodule

counter.v X Vrabcdemux.v x , Untitled 1 X Name Value 999,995 ps 999,996 ps 999,997 ps 999,998 ps 999,999 ps 1,000 04 03 09 0c 0a 2Z 2Z

I will post the synthesized results of this multiplexer tomorrow. As you can see this code is synthesizable.