Question

2atubhs, and explain the cause of oe y LUTs are reqllited l the difference, if any. .37 hekrncecdemux for a customized multiplexer with five 8-bit output bus A. B, C, D, and E, selecting one of the buses to drive a 8-bit nout buses Taccordin jetermine how many internal resources it uses 7 Wnie a Verilog ng to Table X6.47. Synthesize the module for your favorite FPGA as a seven. ding tputs for like the s2 S1 so Input to Select 0 Table X6.47 n mark

Answer 1

//Verilog Code for 8-bit wide 8x1 multiplexer
module Vrabcdemux #(parameter WIDTH = 8) (
input [WIDTH-1:0] A,B,C,D,E, //Input Ports Declaration
input [2:0]S, //Select Line input port Declaration
output reg [WIDTH-1:0] T //Output Port Declaration
);

//Combo Logic for Multiplexer
//Based on select line 'S', mux inputs will be selected for output
always@(*) //For Combo use '*' in always block
begin
case(S)
   3'b000 : T = A;
   3'b001 : T = B;
   3'b010 : T = B;
   3'b011 : T = C;
   3'b100 : T = C;
   3'b101 : T = D;
   3'b110 : T = E;
   3'b111 : T = A;
   endcase
end
endmodule

//Testbench for mux

module test;

reg [7:0]A,B,C,D,E;
reg [2:0]S;
wire [7:0]T;

//Mux module instantiation

Vrabcdemux #(.WIDTH(8)) mux_instance (
.A(A),.B(B),.C(C),.D(D),.E(E),.S(S),.T(T)
       );

//Driving Stimulus
initial begin
A = 10;
B = 20;
C = 30;
D = 40;
E = 50;
S = 0;
#10 S = 1;
#10 S = 2;
#10 S = 3;
#10 S = 4;
#10 S = 5;
#10 S = 6;
#10 S = 7;
#10 S = 8;
#10 $finish;
end
endmodule

//Waveform Simulation

M Modelsim PE Student Edition 104 File Edit View Compile Simulete Add Wave Tools Layout BookmarksWindow Help ILI ■ 豳//..Γ. l Wave -Default sd10 8d20 test test, /tests 8d40 8d50 340 81020 8130 8090 8050 Trarscrpt Library X mdemux.v Now: 90 ns Delta: 0 0 ns to 95 ns

//Synthesis RTL viewer

Ouartus Pnme uite Edition Flle Edit View Project Asslenments Processing Tools Window Help abodemux VWabcdemux Catalog Table of Contents Flow Summary Flow Settings Flow Non-Default Glabal Settir Quartus Prime Version Flow Elapsed Time Flow OS Summary Filter ˇ Installed IP àCyclone IV E:AUTOo Flow Status Successtul Sun Mar 24 2231:43 2019 Project Directory 8.1.0 Build 625 09/12/2018 SJ Lite Edition rabcdemux No Selection Available Y Library Top level Entity Name Family latal lagic elerments Total rogisters Basic Funcions DSP Interface Pratorals Mcmory Interfaces and Controllers Processors and Peripherals EFlow Log > Analysis & Synthesis Cyclone IE Flow Messages Flow Suppressed Messages Total pins 51 latal virtual pins Total memory bits Embedded Multiplier 9-bit elements Iatal PLL Uriversity Prograrn ·5oarch for Partner in 0 Tasks Compilation Task Compile Design Analysis & Synthesis Fitter (Place & Routel Assembler IGenerate programin Timing Analysls EDA Netlist Writer ▼ <> Find.. ee Find Next TVDe ID essage 초 18236 Nu er o processors has not been specified which may cause over olding on shared machines. Set the globa assignment NUM PARALLEL ROCESSORS in your QSF to an appropriate va 0 20030 Parallel compilation is enabled and wi" use 4 of the 4 processors detected 12021 Found 1 design units, including 1 entities, in source file /users/vinay/desktop/vrabcdemux/vrabcdemux.v 12127 Elaborating entity "Vrabcdemux" for the top level hierarchy o 286030 Timing-Driven Synthesis is running 。16010 Generating hard-block partition "hard-block : auto-generated-inst" O 21057 Tmplemented 78 device resources after synthesis - the final resource count might be different Quartus Prine Analysis& Synthesis was successful.o errors.1 warning System Processing (11 100% 00:00:46

RTL Viewer Flle Edit View Tools Mndow Help Page 1 of 1 t Navigator Muxo S12..0 OUT 817.0 C[7.0] DI7.0] Mux1 OUT DAT Mux2 OUT Mux3 OUT Mux4 Mux5 OUT DATAI7.0 Mux6 Mux7 OUT nisplays the previous view 100% 00:00:03