Question

Array Multiplier for Unsigned Number:s (Section 5.6.1) So The array of multiple adders used to compute the partial products is structured like this for a 4-bit multiplier (a) In general, there are n-1 rows in the array for an n-bit multiplier. The top row (b) is structured as shown Fa A ,, , a) Structure of the cirout ろ · Bit of PP And the bottom rows (c) are So structured as shown Now we will go through an example showing how it works FA FA Note: PPn Partial Product n b) A block in the tap raw (c) A black in the batiarn two rows QUESTION 2 Referring to the array multiplier for unsigned numbers in Figure 532 (Slide 5 Module 45) The gate delay to generate my and qy is full-adders The critical path in a 4-bit array multiplier is The total gate delay for a 4-bit array multiplier is If the gate delay is 1/17 ns, how many multiplications can a 4-bit array adder perform per second? nteger with no commas. gates. Enter your answer is an

Answer 1

un ct 4-bi mull i' te delh Fon AND t2 FL OR' 밑 "AB&BC+ CA 8 t2+2t3 CCut. The elgrail m and g Since e re givi in out i each C2) Jhe addu CFA) is tz+2t3 (3 Csitical is dehined as the of an cperation

iven ciacit, citical th is m2 m TD e blck (odderd in the top hoo 40 Cout Cin FA FA Dehay er one bock in bottrm Cout FA Cin

Tolcoy Tf- t-tg and One m a Hock. Sate one block 4 td ns 15 No. of multiplications Pea bec rd·1-12x10