Question

Consider the code sequence below in executing on an SMP system with 2 processors implemented with a snooping bus. The system uses MSI protocol. Assume R2 is initialized to 0x0200 on both processors in cycle C0. ISA format:

opcode <t> <src1> <src2 Cycle CO: C1: C2: C3: C4: С5: Ce: C7: C8: Processor0 Processor 1 nop ld R1, 0(R2) addi R1, 0x72 st R1, 0(R2) mul r1, r3, r4 nop nop nop ld r5, 0(R2) nop nop nop nop ld R1,0(R2) addi R1, 0x72 st R1, 0(R2) nop nop

Fill in the status of the cache line for the address 0x0200 for each cycle for both processors. In MSI protocol, a cache line can be I (Invalid), S (Shared), or M (Modified) state.

Answer 1

Invalid(I)->cache does not have a copy of data.

shared (S)->cache has a read only copy of data.

Modified(M)->cache has an only copy writable.

Id R1,0 (R2)

Id means instruction data.

This command used for memory read data from cache.so this command is specified by 's'.

Addi R1,0x72

addi means add immediate

This command is used to read data from the given location.

st R1,0 (R2)

Reset the data so we can represent with m.

mul r1,r3,r4

apply multiplication on 2 registers and stored in a another register.

so this command write data to the register so it is represented with m.

rop nop Cl ) nop C2. add: R, ,0メわ oddsp , ,0x72. no coch, mne stat, fo 0x200 6