Question

2) In this Problem, we examine the frequency behavior of the source follower stage: VDD Vout bias A) Based on intuition, if we take Cgs, Cgd, Cdb, Cu into account, how many poles does the transfer function have B) Calculate the transfer function H(s) Vout(s)/Vin(s) using small signal model. Do not neglect the channel length modulation effect. (Note: Do not use miller approximation as it is invalid in source follower stage) C) using the result in part (B), calculate H(s) if ro-…. what is the "zero" of H(s). Is it a large or low frequency value? Bonus: Does it remind you of any transistor specifications? D) Calculate the poles in part (D) assuming they are far apart. Hint: if p1 << p2, then(1+:)(1恬)~hh+n+1 E) Using Model-1 transistors, simulate the frequency behavior of a source follower stage. Plot both the magnitude and phase of H(jo). Vdd = 3V, w/L-50um/0.5um, Bias current-1mA, Rs-200Q, C.-100 fF. Use ideal current source in your simulation. Calculate poles and zeros (from part C) and try to verify it with the simulation result. Use the Table in HW1 for the transistor parameters in your calculations.

Answer 1

「regon domain where Trpeda In capacitor foc (sp) Ci30 ) ブin pharor : 5305x10 -90 5 L30 530 5x 10 L-90 q. 424x10 L3019