Regarding Verilog HDL ... You have a timing problem. Looking at the timing report you see that one particular net delay...

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Regarding Verilog HDL ... You have a timing problem. Looking at the timing report you see that one particular net delay...

Regarding Verilog HDL ... You have a timing problem. Looking at the timing report you see that one particular net delay is considerably larger than the other net delays. However, the fanouts are all roughly the same. What is the most likely problem and how would you solve it?

engineering Electrical-Engineering

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Answer 1

Answer #1

For calculating the net delay we have to find out intrinsic resistance and capacitance of the path. It depends upon fan out , length and area of the logic gates. Hence the physical measurements of the wire / logic gate may be higher than the others.

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Answer 2

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Regarding Verilog HDL ... You have a timing problem. Looking at the timing report you see that one particular net delay...

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You have a timing problem. Looking at the timing report you see that one particular net delay is considerably larger tha...

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