Question

(Computer Architecture MIPS Assembly)

Using minimum amount of nops - rewrite the code segment below so it doesn't cause any hazards.
You may not reorder the original instructions, just insert nop where needed.

add $3, $2, $3
lw $4, 100($3)
sub $7, $6, $2
xor $6, $4, $3

Answer 1

Solution:

add $3, $2, $3

nops

nops

lw $4, 100($3)

sub $7, $6, $2

nops

xor $6, $4, $3

Explanation:

First two nops:

The new value of register 3 doesn’t reach the register file until the WB stage of the add instruction, i.e. cycle 5. But the lw instruction needs this value in its ID stage, when it reads register 3. To delay the ID stage of the lw until cycle 5, we need to insert 2 no-ops.

Third nops:

The new value of register 4 doesn’t reach the register file until the WB stage of the lw instruction. If we didn’t insert this no-op, the ID stage of the xor would coincide with the Mem stage of the lw.

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