Question
MIPS
Assembly
Computer Organization and Design

MIPS Algorithm Design (25 pts. Throughout the course, we have learned different types of instruction sets in MIPS programming
0 0
Add a comment Improve this question Transcribed image text
Answer #1

The MIPS instruction set architecture

The MIPS has a 32 bit architecture, with 32 bit instructions, a 32 bit data word, and 32 bit addresses. It has 32 addressable internal registers requiring a 5 bit register address. Register 0 always has the the constant value 0. Addresses are for individual bytes (8 bits) but instructions must have addresses which are a multiple of 4. This is usually stated as “instructions must be word aligned in memory.”

(a)
Total cycles taken by arithmetic operations
2 + 1 + 3 = 6
Total cycles taken by branch operations
2 + 1 + 3 + 2 = 8
Total cycles taken by jump operations
2 + 1 + 1 = 4
Total cycles taken by lw operations
2 + 1 + 3 + 1 + 2 = 9
Total cycles taken by sw operations
2 + 1 + 3 + 1 + 1 = 8

Total cycles = 3*6 + 4*8 + 4 + 9 + 8 = 18 + 32 + 21 = 71
Cycles per instruction (CPI)= 71/10 = 7.1

***********************************************************************************************************************************

In case of any query please ask in the comment section

Add a comment
Know the answer?
Add Answer to:
MIPS Assembly Computer Organization and Design MIPS Algorithm Design (25 pts. Throughout the course, we have...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Q: Assistance in understanding and solving this example on Digital Design and Computer Architecture with the...

    Q: Assistance in understanding and solving this example on Digital Design and Computer Architecture with the steps of the solution to better understand, thanks. a) The fact that several MIPS instructions (collectively called R-type) follow the same format: instruction mnemonic, destination register, first source register, second source register is a reflection of: Design Principle 4 not the right answer Design Principle 3 Design Principle 2 Design Principle 1 b) Which of the four instructions given as choices, correctly matches the...

  • Topics 1. MIPS instruction set architecture (ISA). 2. Performance. 3. MIPS datapath and control. Exercise 1...

    Topics 1. MIPS instruction set architecture (ISA). 2. Performance. 3. MIPS datapath and control. Exercise 1 Consider the memory and register contents shown below. Registers Ox0100 FFF8 13 ($t 5) 14 ($t6) 0x0100 FFFC 0x0101 0000 Memory 0x0000 0000 0x0001 1100 0x0A00 со00 0x1234 4321 OxBAOO OOBB 15 OXAAAA 0000 0x1111 1010 0x7FFF FFFD 0x0100 FFFO 0x0101 0008 (St7) Ox0101 0004 16 ($80) 0x0101 0008 17 ($sl) Show what changes and give the new values in hexadecimal after the following...

  • Consider the following MIPS assembly language instructions: addi $1, $2, 100 swr $1, 0($2): addi $rt,...

    Consider the following MIPS assembly language instructions: addi $1, $2, 100 swr $1, 0($2): addi $rt, $rs, immediate # add immediate swr $rt, immedi ate ($rs) # store word write register These instructions are I-format instructions similar to the load word and store word instructions. The addi and swr instructions store a computed value to the destina- tion register $rt. The instructions do not require any physical hardware changes to the datapath. The effect of each instruction is given below....

  • Write MIPS code for each of the following instructions, Your assembly should implement the C code...

    Write MIPS code for each of the following instructions, Your assembly should implement the C code directly – i.e.,do not ’optimize’ the C code to change the order of operations or reduce computations. Use commands only like add, sub, lw, sw, immediate Part 1. x = 3-13*x; Do not use multiply. One way of doing the multiply without a multiply instruction is by using many add instructions (x+x+...+x). For this problem, you should do it with fewer additions. Hint: We...

  • Processor Hardware Design - MIPS Given this processor hardware design and the control sequence below, describe...

    Processor Hardware Design - MIPS Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy $rt, $rs. when op() op(l) Xyzzy Start: PCout, HARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRoutj IRin Zout, PCin, DUMPonop HALT/* Should end here on undecoded op */ Xyzzy: CONST(-1), Yin SELrs, REGout, ALUxor, Zin Zout, SELrt, REGin, JUMP(Start) Given the xyzzy $rt,$rs instruction as defined above, and assuming that a memory...

  • Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for...

    Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...

  • We have the following sequence of instructions in MIPS lw $t4, 4($s1) or $t1, $t2, $t3...

    We have the following sequence of instructions in MIPS lw $t4, 4($s1) or $t1, $t2, $t3 or $t2, $t1, $t4 or $t1, $t1, $t2 1) Indicate any hazards and what the hazard types are. 2) Assume there is no forwarding in this pipelined processor and each stage takes 1 cycle. Draw the pipeline chart and calculate how many cycles are consumed 3) Assume there is forwarding in this pipelined processor and each stage takes 1 cycle. Draw the pipeline chart...

  • Part A: We wish to add the datapath parts and control needed to implement the jal...

    Part A: We wish to add the datapath parts and control needed to implement the jal (jump and link) instruction. Show the additions to the datapath and control lines of the figure enclosed (Figure 1 below) needed to implement these instructions in the multicycle datapath. There are multiple solutions; choose the solution that minimizes the number of clock cycles for the jal instruction. Part B: Show the additions to the finite state machine of Figure 2 below to implement the...

  • Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with...

    Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with capacity 16384 bytes, 16 bytes block, and a least recently used (LRU) replacement policy. Assume that the cache is empty (all valid bits are 0) before the following code is executed. lw $t1, 0x1040($0) lw $t2, 0x2044($0) lw $t3, 0x3048($0) lw $t4, 0x1044($0) lw $t5, 0x504c($0) lw $t6, 0x3040($0) For each of the six assembly instructions above, state i) the set field value for...

  • How would the multicycle MIPS design support the jr instruction? Show the machine code format and...

    How would the multicycle MIPS design support the jr instruction? Show the machine code format and your solution should describe any new datapath features and control changes to the finite-state diagram below (this may include adding new states). Information for problem1 0 Instruction Fetch 1 Decode/Register Fetch 2 Address Calculation 3 Memory Read 4 Write-back Step 5 Memory Write 6 R-execution 7 R-completion 8 Branch completion 9 Jump completion O Mem Read ALUSelA 0 ALUSelB 01 lorD 0 ALUOp 00...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT