The MIPS instruction set architecture
The MIPS has a 32 bit architecture, with 32 bit instructions, a 32 bit data word, and 32 bit addresses. It has 32 addressable internal registers requiring a 5 bit register address. Register 0 always has the the constant value 0. Addresses are for individual bytes (8 bits) but instructions must have addresses which are a multiple of 4. This is usually stated as “instructions must be word aligned in memory.”
(a)
Total cycles taken by arithmetic operations
2 + 1 + 3 = 6
Total cycles taken by branch operations
2 + 1 + 3 + 2 = 8
Total cycles taken by jump operations
2 + 1 + 1 = 4
Total cycles taken by lw operations
2 + 1 + 3 + 1 + 2 = 9
Total cycles taken by sw operations
2 + 1 + 3 + 1 + 1 = 8
Total cycles = 3*6 + 4*8 + 4 + 9 + 8 = 18 + 32 + 21 = 71
Cycles per instruction (CPI)= 71/10 = 7.1
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MIPS Assembly Computer Organization and Design MIPS Algorithm Design (25 pts. Throughout the course, we have...
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Processor Hardware Design - MIPS
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Part A: We wish to add the datapath parts and
control needed to implement the jal (jump and
link) instruction. Show the additions to the datapath and control
lines of the figure enclosed (Figure 1 below) needed to implement
these instructions in the multicycle datapath. There are multiple
solutions; choose the solution that minimizes the number of clock
cycles for the jal instruction.
Part B: Show the additions to the finite state
machine of Figure 2 below to implement the...
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Show the machine code format and your solution should describe any
new datapath features and control changes to the finite-state
diagram below (this may include adding new states).
Information for problem1 0 Instruction Fetch 1 Decode/Register Fetch 2 Address Calculation 3 Memory Read 4 Write-back Step 5 Memory Write 6 R-execution 7 R-completion 8 Branch completion 9 Jump completion O Mem Read ALUSelA 0 ALUSelB 01 lorD 0 ALUOp 00...