(PALs) Implement an 8-bit register using the 20X10 PAL of Figure 9.20 to the following spe...

(PALs) Implement an 8-bit register using the 20X10 PAL of Figure 9.20 to the following specifications:

(a) The register has three control inputs, (output enable), (load), and CLK (clock), and eight data inputs D7−D0. It has eight registered outputs Q7−Q0. When is unasserted, the outputs are in high impedance. When is unasserted, the register holds its current value. When is asserted, the register’s contents are replaced by the data inputs on the next rising clock edge. What are the Boolean equations for each register input? Draw a wiring diagram, similar to Figure 9.18, for the PAL’s pin inputs and outputs.

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(b) The register has three control inputs: (output enable), (clear/increment), and CLK (clock), and eight data outputs, Q7−Q0. When is unasserted, the outputs are in high impedance. When CLR is asserted, the register is set to 0 on the next rising clock edge. When CLR is unasserted, the register is incremented by 1 on the next clock edge. In essence, the register is a free-running counter. What are the Boolean equations for each register input? Draw a wiring diagram like Figure 9.18 for the PAL’s pin inputs and outputs. (Hint: Consider the carry-lookahead logic described in Chapter 5, except simplified for the specific case where the sum is A + 1.)